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PC7447 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer PC7447
Beschreibung (PC7447 / PC7457) PowerPC 7457 RISC Microprocessor
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 30 Seiten
PC7447 Datasheet, Funktion
Features
3000 Dhrystone 2.1 MIPS at 1.3 GHz
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
13 Selectable Core-to-L3 Frequency Divisors
Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
Selectable L3 Interface of 1.8V or 2.5V
PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating
Conditions
Nap, Doze and Sleep Modes for Power Saving
Superscalar (Four Instructions Fetched Per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 Hexabytes (252)
64-bit Data and 32-bit Address Bus Interface
Integrated L1: 32 KB Instruction and 32 KB Data Cache
Integrated L2: 512 KB
11 Independent Execution Units and Three Register Files
Write-back and Write-through Operations
fINT Max = 1 GHz (1.2 GHz to be Confirmed)
fBUS Max = 133 MHz/166 MHz
Description
This document is primarily concerned with the PowerPCPC7457; however, unless
otherwise noted, all information here also applies to the PC7447. The PC7457 and
PC7447 are implementations of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the PC7457.
The PC7457 is the fourth implementation of the fourth generation (G4) microproces-
sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and
is targeted at networking and computing systems applications. The PC7457 consists
of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup-
port a glueless backside L3 cache through a dedicated high-bandwidth interface. The
PC7447 is identical to the PC7457 except it does not support the L3 cache interface.
The core is a high-performance superscalar design supporting a double-precision
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-
ports the MPX bus interface to main memory and other system resources. The L3
interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private
memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes
may be used as cache; the remaining 2M bytes must be private memory.
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455
application if the core power supply is 1.3V.
PowerPC 7457
RISC
Microprocessor
PC7457/47
Preliminary
Specification
α-site
Rev. 5345B–HIREL–02/04






PC7447 Datasheet, Funktion
Performs alignment, normalization, and precision conversion for floating-
point data
Executes cache control and TLB instructions
Performs alignment, zero padding, and sign extension for integer data
Supports hits under misses (multiple outstanding misses)
Supports both big- and little-endian modes, including misaligned little-endian
accesses
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three
instructions, respectively, in a cycle. Instruction dispatch requires the following:
– Instructions can be dispatched only from the three lowest IQ entries – IQ0,
IQ1, and IQ2
– A maximum of three instructions can be dispatched to the issue queues per
clock cycle
– Space must be available in the CQ for an instruction to dispatch (this
includes instructions that are assigned a space in the CQ but not in an issue
queue)
• Rename buffers
– 16 GPR rename buffers
– 16 FPR rename buffers
– 16 VR rename buffers
• Dispatch unit
– Decode/dispatch stage fully decodes each instruction
• Completion unit
– The completion unit retires an instruction from the 16-entry completion
queue (CQ) when all instructions ahead of it have been completed, the
instruction has finished execution, and no exceptions are pending
– Guarantees sequential programming model (precise exception model)
– Monitors all dispatched instructions and retires them in order
– Tracks unresolved branches and flushes instructions after a mispredicted
branch
– Retires as many as three instructions per clock cycle
• Separate on-chip L1 Instruction and data caches (Harvard Architecture)
– 32 Kbyte, eight-way set-associative instruction and data caches
– Pseudo least-recently-used (PLRU) replacement algorithm
– 32-byte (eight-word) L1 cache block
– Physically indexed/physical tags
– Cache write-back or write-through operation programmable on a per-page or
per-block basis
– Instruction cache can provide four instructions per clock cycle; data cache
can provide four words per clock cycle
– Caches can be disabled in software
– Caches can be locked in software
6 PC7457/47 [Preliminary]
5345B–HIREL–02/04

6 Page









PC7447 pdf, datenblatt
7. L3VSEL must be set to 0, such that the bus is in 1.8V mode.
8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
9. Caution: VIN must not exceed OVDD or GVDD by more than 0.3V at any time including during power-on reset.
10. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
Recommended
Operating Conditions
Table 3. Recommended Operating Conditions(1)
Recommended Value
Symbol Characteristic
Min Max Unit
VDD
AVDD(2)
Core supply voltage
PLL supply voltage
1.3V ±50 mV or 1.1V ±50 mV
1.3V ±50 mV or 1.1V ±50 mV
V
V
OVDD
OVDD
Processor bus supply voltage
BVSEL = 0
BVSEL = HRESET or OVDD
1.8V ±5%
2.5V ±5%
V
V
GVDD
L3VSEL = 0
1.8V ±5%
V
GVDD
GVDD(3)
L3 bus supply voltage
L3VSEL = HRESET or GVDD
L3VSEL = ¬HRESET
2.5V ±5%
1.5V ±5%
V
V
VIN
Processor bus
GND
OVDD
V
VIN Input voltage
L3 bus
GND
GVDD
V
VIN
JTAG signals
GND
OVDD
V
Tj
Notes:
Die-junction temperature
-55 125 °C
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
2. This voltage is the input to the filter discussed in Section “PLL Power Supply Filtering” on page 54 and not necessarily the
voltage at the AVDD pin which may be reduced from VDD by the filter.
3. ¬HRESET is the inverse of HRESET.
Figure 3. Overshoot/Undershoot Voltage
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD/GVDD
VIH
VIL
GND
GND – 0.3V
GND – 0.7V
12 PC7457/47 [Preliminary]
Not to exceed 10% of tSYSCLK
5345B–HIREL–02/04

12 Page





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