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D7225G Schematic ( PDF Datasheet ) - NEC

Teilenummer D7225G
Beschreibung UPD7225G
Hersteller NEC
Logo NEC Logo 




Gesamt 52 Seiten
D7225G Datasheet, Funktion
www.DataSheet4U.com
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD7225
PROGRAMMABLE LCD CONTROLLER/DRIVER
The µPD7225 is a software-programmable LCD (Liquid Crystal Display) controller/driver. The µPD7225 can be
serially interfaced with the CPU in a microcomputer and can directly drive 2, 3, or 4-time division LCD. The µPD7225
contains a segment decoder which can generate specific segment patterns. In addition, the µPD7225 can be used to
control on/off (blinking) operation of a display.
FEATURES
• Can directly drive LCD
• Programmable time-division multiplexing
Static drive
Divide-by-2, 3, or -4 time division multiplexing
• Number of digits displayed
7-segment
Divide-by-4 time division ............... 16 digits
Divide-by-3 time division ............... 10 2/3 digits
Divide-by-2 time division ............... 8 digits
Static................................................. 4 digits
14-segment
Divide-by-4 time division ............... 8 digits
• Bias method
Static, 1/2, 1/3
• Segment decoder output
7-segment : Numeric characters 0 to 9, six symbols
14-segment : 36 alphanumeric characters, 13 symbols
• Blinking operation
• Multi-chip configuration possible
• 8-bit serials interface
75X series and 78K series compatible
• CMOS
• Single power supply
ORDERING INFORMATION
Part Number
µPD7225G00
µPD7225G01
µPD7225GB-3B7
µPD7225GC-AB6
Package
52-pin plastic QFP (14 × 14 mm)
52-pin plastic QFP (straight) ( 14 mm)
56-pin plastic QFP (10 × 10 mm)
52-pin plastic QFP (14 × 14 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14308EJ6V0DS00 (6th edition)
(O.D. No. IC-1555)
Date Published June 1999 N CP (K)
Printed in Japan
The mark shows major revised points.
©
1986, 1999






D7225G Datasheet, Funktion
www.DataSheet4U.com
Static
Figure 1-2. /SYNC Pin Status after Reset (/RESET = 1)
1 frame
µPD7225
COM0
/SYNC
Divie-by-2
time division
COM0
/SYNC
Divie-by-3
time division
COM0
/SYNC
Divie-by-4
time division
COM0
/SYNC
1 frame
1 frame
1 frame
1.7 /RESET……Input
This is an active low reset input pin.
1.8 S0-S31 (Segment)……Output
These pins output segment drive signals.
1.9 COM0-COM3 (COMmon)……Output
These pins output common drive signals.
1.10 CL1, CL2 (Clock)
A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the
CL1 pin for input.
1.11 VLC1, VLC2, VLC3
LCD driver power supply pin.
6 Data Sheet S14308EJ6V0DS00

6 Page









D7225G pdf, datenblatt
www.DataSheet4U.com
µPD7225
Figure 2-3. 7-Segment LCD
Data
(HEX)
Display
pattern
Data memory
Divide-by-3 Divide-by-4
time division time division
N +2 N +1 N N +1 N
Data
(HEX)
Display
pattern
Data memory
Divide-by-3 Divide-by-4
time division time division
N +2 N +1 N N +1 N
00
3 53
D7
08
3 73
F7
01
0 03
06
09
1 73
B7
02
2 71
E3
0A
0 20
20
03
0 73
A7
0B
3 70
F1
04
1 23
36
0C
3 50
D1
05
1 72
B5
0D
0 60
A0
06
3 72
F5
0E
2 62
E4
07
0 13
07
0F
0 00
00
12 Data Sheet S14308EJ6V0DS00

12 Page





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