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Número de pieza | ECLSOIC8EVB | |
Descripción | Evaluation Board Manual for High Frequency SOIC 8 | |
Fabricantes | ON Semiconductor | |
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No Preview Available ! ECLSOIC8EVB
Evaluation Board Manual
for High Frequency SOIC 8
http://onsemi.com
EVALUATION BOARD MANUAL
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 8−lead SOIC package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 8−lead SOIC device
samples. The board provides a high bandwidth 50 W
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways, depending on
device under test (See Table 1. Configuration List).
This evaluation board manual contains:
• Information on 8−lead SOIC Evaluation Board
• Assembly Instructions
• Appropriate Lab Setup
• Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−Up
The 8−lead SOIC evaluation board is implemented in four
layers with split (dual) power supplies (Figure 2.
Evaluation Board Lay−up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the
50 W internal impedance in the oscilloscope as a termination
for ECL devices. The first layer or primary trace layer is
0.008″ thick Rogers RO4003 material, which is designed to
have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground plane and a portion of the
plane is the VEE power plane. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is also 1.0 oz copper ground
plane and a portion of this layer is VCC power plane. The
fourth layer is the secondary trace layer.
Figure 1. Top and Bottom View of the 8−lead SOIC Evaluation Board
© Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 1
1
Publication Order Number:
ECLSOIC8EVB/D
1 page CONFIGURATIONS
ECLSOIC8EVB
VCC GND
C4
0.1 mF
R1
50 W
J1
C1
0.01 mF
R2
50 W
DUT
J2
J5
R3
50 W
J3
C2
0.01 mF
J6
R4
50 W
J4
C3
0.1 mF
VEE GND
Figure 4. Configuration 1 Schematic
Table 4. Configuration 1
Device
MC10EL01D/MC100EL01D
MC10EL05D/MC100EL05D
MC10EL31D/MC100EL31D
MC10EL35D/MC100EL35D
MC10EL51D/MC100EL51D
MC10EL52D/MC100EL52D
MC100LVEL01D
MC100LVEL05D
MC100LVEL31D
MC100LVEL51D
MC10EP01D/MC100EP01D
MC10EP05D/MC100EP05D
MC10EP08D/MC100EP08D
MC10EP31D/MC100EP31D
MC10EP35D/MC100EP35D
MC10EP51D/MC100EP51D
MC10EP52D/MC100EP52D
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes
http://onsemi.com
5
5 Page ECLSOIC8EVB
VCC GND
C4
0.1 mF
Pin 1 Pin 8
C1
0.01 mF
R2 Pin 2 Pin 7
50 W
DUT
J2
R3 Pin 3 Pin 6
50 W
J3
J7
Pin 4 Pin 5
Short
VEE GND
Figure 10. Configuration 7 − Translator Schematic
(Unloaded Testing Condition)
Table 10. Configuration 7
Pin 1
Pin 2
Pin 3
Pin 4
Device
J1 R1 J2 R2 J3 R3 J4 R4
MC10ELT21D/MC100EL21D
MC100EPT21D
No No Yes Yes Yes Yes No No
*See Appendix for loaded testing condition.
Pin 5
C2 C3
No No
Pin 6
J6 R6
No No
Pin 7
Pin 8
J7 R7 C1 C4
Yes No Yes Yes
http://onsemi.com
11
11 Page |
Páginas | Total 20 Páginas | |
PDF Descargar | [ Datasheet ECLSOIC8EVB.PDF ] |
Número de pieza | Descripción | Fabricantes |
ECLSOIC8EVB | Evaluation Board Manual for High Frequency SOIC 8 | ON Semiconductor |
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