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EBD51RC4AKFA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBD51RC4AKFA
Beschreibung 512MB Registered DDR SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 19 Seiten
EBD51RC4AKFA Datasheet, Funktion
DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RC4AKFA (64M words × 72 bits, 1 Rank)
Description
The EBD51RC4AKFA is a 64M words × 72 bits, 1 rank
Double Data Rate (DDR) SDRAM Module, mounting 18
pieces of DDR SDRAM sealed in TSOP package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2-bit prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology. Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 2 pieces of register
drivers and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD)
Document No. E0377E20 (Ver. 2.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003-2004






EBD51RC4AKFA Datasheet, Funktion
EBD51RC4AKFA
Byte No.
28
29
30
Function described
Minimum row active to row active
delay (tRRD)
-6B
-7A, -7B
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
Minimum active to precharge time
(tRAS)
-6B
-7A, -7B
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 1 1 0 0 0 0 30H
0 0 1 1 1 1 0 0 3CH
0 1 0 0 1 0 0 0 48H
0 1 0 1 0 0 0 0 50H
0 0 1 0 1 0 1 0 2AH
0 0 1 0 1 1 0 1 2DH
31 Module rank density
1 0 0 0 0 0 0 0 80H
Address and command setup time
32 before clock (tIS)
0 1 1 1 0 1 0 1 75H
-6B
-7A, -7B
1 0 0 1 0 0 0 0 90H
Address and command hold time after
33 clock (tIH)
0 1 1 1 0 1 0 1 75H
-6B
-7A, -7B
1 0 0 1 0 0 0 0 90H
Data input setup time before clock
34 (tDS)
0 1 0 0 0 1 0 1 45H
-6B
-7A, -7B
0 1 0 1 0 0 0 0 50H
35
Data input hold time after clock (tDH)
-6B
0
1
0
0
0
1
0
1
45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
36 to 40 Superset information
0 0 0 0 0 0 0 0 00H
41
Active command period (tRC)
-6B
0 0 1 1 1 1 0 0 3CH
-7A, -7B
0 1 0 0 0 0 0 1 41H
Auto refresh to active/
42 Auto refresh command cycle (tRFC) 0 1 0 0 1 0 0 0 48H
-6B
-7A, -7B
0 1 0 0 1 0 1 1 4BH
43 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H
44
Dout to DQS skew
-6B
0 0 1 0 1 1 0 1 2DH
-7A, -7B
0 0 1 1 0 0 1 0 32H
45
Data hold skew (tQHS)
-6B
0 1 0 1 0 1 0 1 55H
-7A, -7B
0 1 1 1 0 1 0 1 75H
46 to 61 Superset information
0 0 0 0 0 0 0 0 00H
62 SPD revision
63
Checksum for bytes 0 to 62
-6B
-7A
0 0 0 0 0 0 0 0 00H
0 1 0 1 0 0 0 1 51H
0 0 0 0 1 0 0 0 08H
-7B 0 0 1 1 0 0 1 1 33H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
66
Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
Comments
12ns
15ns
18ns
20ns
42ns
45ns
1 rank
512MB
0.75ns*3
0.9ns*3
0.75ns*3
0.9ns*3
0.45ns*3
0.5ns*3
0.45ns*3
0.5ns*3
Future use
60ns*3
65ns*3
72ns*3
75ns*3
12ns*3
0.45ns*3
0.5ns*3
0.55ns*3
0.75ns*3
Future use
Initial
81
8
51
Continuation
code
Elpida Memory
Data Sheet E0377E20 (Ver. 2.0)
6

6 Page









EBD51RC4AKFA pdf, datenblatt
EBD51RC4AKFA
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE
15
pF 1, 3
Input capacitance
CI2 CK, /CK
20 pF 1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB
15
pF 1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM component Specification)
-6B -7A
Parameter
Symbol min.
max.
Clock cycle time
(CL = 2)
(CL = 2.5)
tCK 7.5
tCK 6
12
12
CK high-level width
tCH 0.45
0.55
CK low-level width
tCL 0.45
CK half period
DQ output access time from
CK, /CK
tHP
min
(tCH, tCL)
tAC –0.7
DQS output access time from CK, /CK tDQSCK –0.6
0.55
0.7
0.6
DQS to DQ skew
tDQSQ —
0.45
DQ/DQS output hold time from DQS tQH
tHP – tQHS —
Data hold skew factor
tQHS
Data-out high-impedance time from
CK, /CK
tHZ
Data-out
/CK
low-impedance
time
from
CK,
tLZ
Read preamble
tRPRE
–0.7
–0.7
0.9
0.55
0.7
0.7
1.1
Read postamble
tRPST 0.4
0.6
DQ and DM input setup time
tDS 0.45
DQ and DM input hold time
tDH 0.45
DQ and DM input pulse width
tDIPW 1.75
Write preamble setup time
tWPRES 0
Write preamble
tWPRE 0.25
Write postamble
Write command to first DQS latching
transition
DQS falling edge to CK setup time
tWPST 0.4
tDQSS 0.75
tDSS 0.2
0.6
1.25
DQS falling edge hold time from CK tDSH 0.2
DQS input high pulse width
tDQSH 0.35
DQS input low pulse width
tDQSL 0.35
Address and control input setup time tIS
0.75
Address and control input hold time tIH
0.75
min. max.
7.5 12
7.5
0.45
0.45
min
(tCH, tCL)
12
0.55
0.55
–0.75
0.75
–0.75
0.75
— 0.5
tHP – tQHS —
— 0.75
–0.75
0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.9
0.75
1.1
0.6
0.6
1.25
-7B
min. max.
10 12
7.5 12
0.45 0.55
0.45
min
(tCH, tCL)
0.55
–0.75
0.75
–0.75
0.75
— 0.5
tHP – tQHS —
— 0.75
–0.75
0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.9
0.75
1.1
0.6
0.6
1.25
Unit Notes
ns 10
ns
tCK
tCK
tCK
ns 2, 11
ns 2, 11
ns 3
ns
ns
ns 5, 11
ns 6, 11
tCK
tCK
ns 8
ns 8
ns 7
ns
tCK
tCK 9
tCK
tCK
tCK
tCK
tCK
ns 8
ns 8
Data Sheet E0377E20 (Ver. 2.0)
12

12 Page





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