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EBD52UD6ADSA-E Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBD52UD6ADSA-E
Beschreibung 512MB DDR SDRAM SO-DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 19 Seiten
EBD52UD6ADSA-E Datasheet, Funktion
DATA SHEET
512MB DDR SDRAM SO-DIMM
EBD52UD6ADSA-E (64M words × 64 bits, 2 Ranks)
Description
The EBD52UD6ADSA is 64M words × 64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 8 pieces of 512M
bits DDR SDRAM sealed in TSOP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
Lead-free
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs and DM are synchronized with
DQS
4 internal banks for concurrent operation
(Components)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
Document No. E0604E10 (Ver. 1.0)
Date Published October 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2004






EBD52UD6ADSA-E Datasheet, Funktion
EBD52UD6ADSA-E
Byte No. Function described
29
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
Minimum active to precharge time
30 (tRAS)
-6B
-7A, -7B
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 1 0 0 1 0 0 0 48H
0 1 0 1 0 0 0 0 50H
0 0 1 0 1 0 1 0 2AH
0 0 1 0 1 1 0 1 2DH
31 Module rank density
0 1 0 0 0 0 0 0 40H
Address and command setup time
32 before clock (tIS)
0 1 1 1 0 1 0 1 75H
-6B
-7A, -7B
1 0 0 1 0 0 0 0 90H
Address and command hold time after
33 clock (tIH)
0 1 1 1 0 1 0 1 75H
-6B
-7A, -7B
1 0 0 1 0 0 0 0 90H
34
Data input setup time before clock (tDS)
-6B
0
1
0
0
0
1
0
1
45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
35
Data input hold time after clock (tDH)
-6B
0
1
0
0
0
1
0
1
45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
36 to 40 Superset information
0 0 0 0 0 0 0 0 00H
41
Active command period (tRC)
-6B
0 0 1 1 1 1 0 0 3CH
-7A, -7B
0 1 0 0 0 0 0 1 41H
Auto refresh to active/
42 Auto refresh command cycle (tRFC) 0 1 0 0 1 0 0 0 48H
-6B
-7A, -7B
0 1 0 0 1 0 1 1 4BH
43
SDRAM tCK cycle max. (tCK max.)
0 0 1 1 0 0 0 0 30H
44
Dout to DQS skew
-6B
0 0 1 0 1 1 0 1 2DH
-7A, -7B
0 0 1 1 0 0 1 0 32H
45
Data hold skew (tQHS)
-6B
0 1 0 1 0 1 0 1 55H
-7A, -7B
0 1 1 1 0 1 0 1 75H
46 to 61 Superset information
0 0 0 0 0 0 0 0 00H
62 SPD Revision
63
Checksum for bytes 0 to 62
-6B
-7A
0 0 0 0 0 0 0 0 00H
0 0 0 0 1 0 0 1 09H
1 1 0 0 0 0 0 0 C0H
-7B 1 1 1 0 1 0 1 1 EBH
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
66 Manufacturer’s JEDEC ID code
67 to 71 Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
72 Manufacturing location
× × × × × × × × ××
73 Module part number
74 Module part number
0 1 0 0 0 1 0 1 45H
0 1 0 0 0 0 1 0 42H
Comments
18ns
20ns
42ns
45ns
256M bytes ×
2 ranks
0.75ns*1
0.9ns*1
0.75ns*1
0.9ns*1
0.45ns*1
0.5ns*1
0.45ns*1
0.5ns*1
Future use
60ns*1
65ns*1
72ns*1
75ns*1
12ns*1
0.45ns*1
0.5ns*1
0.55ns*1
0.75ns*1
Future use
Continuation
code
Elpida Memory
(ASCII-8bit
code)
E
B
Data Sheet E0604E10 (Ver. 1.0)
6

6 Page









EBD52UD6ADSA-E pdf, datenblatt
EBD52UD6ADSA-E
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Input capacitance
Input capacitance
Data and DQS input/output
capacitance
Symbol
CI1
CI2
CO
Pins
Address, /RAS, /CAS, /WE
CK, /CK, CKE, /CS
DQ, DQS, DM
max.
60
50
20
Unit Note
pF
pF
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B -7A
Parameter
Symbol min.
max.
Clock cycle time
(CL = 2)
(CL = 2.5)
tCK 7.5
tCK 6
12
12
CK high-level width
tCH 0.45
0.55
CK low-level width
tCL
CK half period
tHP
DQ output access time from
CK, /CK
tAC
DQS output access time from CK,
/CK
tDQSCK
DQS to DQ skew
tDQSQ
DQ/DQS output hold time from
DQS
tQH
Data hold skew factor
tQHS
Data-out high-impedance
CK, /CK
time
from
tHZ
Data-out low-impedance time from
CK, /CK
tLZ
Read preamble
tRPRE
0.45
min
(tCH, tCL)
0.55
–0.7 0.7
–0.6 0.6
— 0.45
tHP – tQHS —
— 0.55
–0.7 0.7
–0.7 0.7
0.9 1.1
Read postamble
tRPST 0.4
0.6
DQ and DM input setup time
tDS 0.45
DQ and DM input hold time
tDH 0.45
DQ and DM input pulse width
tDIPW 1.75
Write preamble setup time
tWPRES 0
Write preamble
tWPRE 0.25
Write postamble
tWPST
Write command to first DQS
latching transition
tDQSS
DQS falling edge to CK setup time tDSS
DQS falling edge hold time from
CK
tDSH
DQS input high pulse width
tDQSH
0.4
0.75
0.2
0.2
0.35
0.6
1.25
DQS input low pulse width
tDQSL
Address and control input setup
time
tIS
Address and control input hold time tIH
Address and control input pulse
width
tIPW
0.35
0.75
0.75
2.2
min. max.
7.5 12
7.5
0.45
0.45
min
(tCH, tCL)
12
0.55
0.55
–0.75
0.75
–0.75
0.75
— 0.5
tHP – tQHS —
— 0.75
–0.75
0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.9
2.2
0.75
1.1
0.6
0.6
1.25
-7B
min. max
10 12
7.5 12
0.45 0.55
0.45
min
(tCH, tCL)
0.55
–0.75
0.75
–0.75
0.75
— 0.5
tHP – tQHS —
— 0.75
–0.75
0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.9
2.2
0.75
1.1
0.6
0.6
1.25
Unit Notes
ns 10
ns
tCK
tCK
tCK
ns 2, 11
ns 2, 11
ns 3
ns
ns
ns 5, 11
ns 6, 11
tCK
tCK
ns 8
ns 8
ns 7
ns
tCK
tCK 9
tCK
tCK
tCK
tCK
tCK
ns 8
ns 8
ns 7
Data Sheet E0604E10 (Ver. 1.0)
12

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