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WEDPN4M72V Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WEDPN4M72V
Beschreibung 4M x 72 SDRAM
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 14 Seiten
WEDPN4M72V Datasheet, Funktion
White Electronic Designs
WEDPN4M72V-XBX
4Mx72 Synchronous DRAM*
FEATURES
High Frequency = 100, 125MHz
Package:
*219 Plastic Ball Grid Array (PBGA), 25 x 21mm
DSingle 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
Eedge of system clock cycle
Internal pipelined operation; column address can be
Dchanged every clock cycle
Internal banks for hiding row access/precharge
NProgrammable Burst length 1,2,4,8 or full page
E4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
MOrganized as 4M x 72
Weight: WEDPN4M72V-XBX - 2 grams typical
MBENEFITS
O60% SPACE SAVINGS
CReduced part count
Reduced I/O count
E19% I/O Reduction
w Lower inductance and capacitance for low noise
w Rperformance
Suitable for hi-reliability applications
w TUpgradeable to 8M x 72 density with same footprint
(contact factory for information)
.DO* This product is Not Recommended for New Designs, refer to WEDPN4M72V-XB2X
for new designs.
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
Nata Discrete Approach
S 11.9 11.9 11.9 11.9
11.9
he54
e22.3 TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
t4UArea
5 x 265mm2 = 1328mm 2
.cI/O
oCount
5 x 54 pins = 270 pins
mWhite Electronic Designs Corp. reserves the right to change products or specifications without notice.
ACTUAL SIZE
White Electronic Designs
WEDPN4M72V-XBX
21
25
S
A
V
I
N
G
S
525mm 2
60%
219 Balls 19%
April, 2004
Rev. 15
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WEDPN4M72V Datasheet, Funktion
White Electronic Designs
WEDPN4M72V-XBX
CK
COMMAND
I/O
FIG. 3 – CAS LATENCY
T0 T1 T2 T3
READ
NOP
tLZ
tAC
CAS Latency = 2
NOP
OH
DOUT
CK
COMMAND
T0
READ
I/O
T1 T2 T3 T4
NOP
NOP
tLZ
tAC
CAS Latency = 3
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
SPEED
-100
-125
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
CAS
LATENCY = 3
75 100
100
125
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2004
Rev. 15
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WEDPN4M72V pdf, datenblatt
White Electronic Designs
WEDPN4M72V-XBX
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
Parameter/Condition
READ/WRITE command to READ/WRITE command (17)
CKE to clock disable or power-down entry mode (14)
CKE to clock enable or power-down exit setup mode (14)
DQM to input data delay (17)
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay (17)
Data-in to ACTIVE command (15)
Data-in to PRECHARGE command (16)
Last data-in to burst STOP command (17)
Last data-in to new READ/WRITE command (17)
Last data-in to PRECHARGE command (16)
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
Data-out to high-impedance from PRECHARGE command (17)
CL = 3
CL = 2
Symbol
tCCD
tCKED
tPED
tDQD
tDQM
tDQZ
tDWD
tDAL
tDPL
tBDL
tCDL
tRDL
tMRD
tROH
tROH
-100 -125
11
11
11
00
00
22
00
45
22
11
11
22
22
33
2—
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100ms is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC must
be powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to
1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are otherwise at valid VIH or VIL levels.
13. ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the
fact that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN)
= -2V for a pulse width 3ns.
22. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2004
Rev. 15
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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