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DPS128M8xxx Schematic ( PDF Datasheet ) - Dense-Pac Microsystems

Teilenummer DPS128M8xxx
Beschreibung 128kx8 High Speed CMOS SRAM
Hersteller Dense-Pac Microsystems
Logo Dense-Pac Microsystems Logo 




Gesamt 10 Seiten
DPS128M8xxx Datasheet, Funktion
1 Megabit High Speed CMOS SRAM
DPS128M8CnY/BnY, DPS128X8CA3/BA3
DESCRIPTION:
The DPS128M8CnY/BnY, DPS128X8CA3/BA3 High Speed SRAM
devices are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages,
or mounted on a 50-pin PGA co-fired ceramic substrate. These devices
pack 1-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in2, while maintaining a total height as low as 0.082 inches.
The SLCC devices contain an individual 128K x 8 SRAMs, each
packaged in a hermetically sealed SLCC, making the modules suitable
for commercial, industrial and military applications.
The DPS128M8BnY/DPS128X8BA3 has one active low Chip Enable
(CE) while the DPS128M8CnY/DPS128X8CA3 has an active low Chip
Enable (CE) and an active high Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC
‘’I’’ Leaded
SLCC
FEATURES:
Organization Available: 128Kx8
Access Times: 20*, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply, ±10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage: 2.0V min.
Packages Available:
‘’J’’ Leaded
SLCC
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin ‘’J’’ Leaded SLCC
48 - Pin Gullwing Leaded SLCC
50 - Pin PGA Dense-Stack
w * Commercial only.
ww. Dense-Stack
Gullwing
Leaded SLCC
DataSheet430A097-31
U.comREV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1






DPS128M8xxx Datasheet, Funktion
DPS128M8CnY/BnY, DPS128X8CA3/BA3
Dense-Pac Microsystems, Inc.
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges
No. Symbol
Parameter
20ns*
Min. Max.
25ns
Min. Max.
30ns
Min. Max.
35ns
Min. Max.
45ns
Min. Max.
Unit
13 tWC Write Cycle Time
20 25 30 35 45 ns
14 tAW Address Valid to End of Write
15 20 25 30 40 ns
15 tCW Chip Enable to End of Write
15 20 25 30 40 ns
16 tAS Address Set-Up Time **
0 0 0 0 0 ns
17 tWP Write Pulse Width
15 20 25 30 35 ns
18 tWR Write Recovery Time
0 0 0 0 0 ns
19 tWHZ Write Enable to Output in HIGH-Z 4, 5
8 10 12 15 20 ns
20 tDW Data to Write Time Overlap
12 15 15 20 25 ns
21 tDH Data Hold from Write Time
0 0 0 0 0 ns
22 tOW Output Active from End of Write 3 3 3 3 3 ns
* Available in Commercial Only.
** Valid for both Read and Write Cycles.
WRITE CYCLE 1: CE Controlled. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at
DC level).
3. Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of ±500mV from steady state
voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in
the output state,and input signals of opposite phase to the
outputs must not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. SEL timing is the same as CE timing (Valid for DPS128M8CnY/
DPS128CA3 only). The Waveform is inverted.
9. Chip Enable and Write Enable can initiate and terminate
WRITE Cycle.
6 30A097-31
REV. D

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