Datenblatt-pdf.com


DPS128C32BV3 Schematic ( PDF Datasheet ) - Dense-Pac Microsystems

Teilenummer DPS128C32BV3
Beschreibung 512kx8 High Speed CMOS SRAM
Hersteller Dense-Pac Microsystems
Logo Dense-Pac Microsystems Logo 




Gesamt 7 Seiten
DPS128C32BV3 Datasheet, Funktion
4 Megabit High Speed CMOS SRAM
DPS128C32BV3
DESCRIPTION:
The DPS128C32BV3 ‘’VERSA-STACK’’ module is a
revolutionary new high speed memory subsystem using
Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC) mounted on a co-fired ceramic substrate.
It offers 4 Megabits of SRAM in a package envelope of
1.090 x 1.090 x 0.300 inches.
The DPS128C32BV3 contains four individual 128K x 8
SRAMs, packaged in their own hermetically sealed SLCCs
making the module suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers
a higher board density of memory than available with
conventional through-hole, surface mount, module, or
hybrid techniques.
FEATURES:
Organizations Available:
128K x 32, 256K x 16, or
512K x 8
Access Times:
20, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Single +5V Power Supply,
±10% Tolerance
TTL Compatible
FUNCTIONAL BLOCK DIAGRAM
Common Data Inputs
and Outputs
Low Data Retention Voltage:
2.0V min.
66-Pin PGA ‘’VERSA-STACK’’
w Package
w * Commercial only.
w. PIN NAMES
D A0 - A16
aI/O0 - I/O31
CE0 - CE3
taWE0 - WE3
OE
SVDD
hVSS
eN.C.
Address Inputs
Data Input/Output
Chip Enables
Write Enables
Output Enable
Power (+5V)
Ground
No Connect
PIN-OUT DIAGRAM
et30A044-28
4U.comREV. F
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change products or specifications herein without prior notice.
1






DPS128C32BV3 Datasheet, Funktion
DPS128C32BV3
Dense-Pac Microsystems, Inc.
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3: WE Controlled. OE is LOW. 8
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level).
3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of ±500mV from steady state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
Data Valid
6
WAVEFORM KEY
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A044-28
REV. F

6 Page







SeitenGesamt 7 Seiten
PDF Download[ DPS128C32BV3 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
DPS128C32BV3512kx8 High Speed CMOS SRAMDense-Pac Microsystems
Dense-Pac Microsystems

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche