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P4NB100 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer P4NB100
Beschreibung STP4NB100
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 9 Seiten
P4NB100 Datasheet, Funktion
www.DataSheet4U.com
STP4NB100
® STP4NB100FP
N - CHANNEL 1000V - 4- 3.8A - TO-220/TO-220FP
PowerMESHMOSFET
TYPE
VDSS
RDS(on)
ID
ST P4NB1 00
1000 V
STP4NB100FP 1000 V
< 4.4
< 4.4
3.8 A
3.8 A
s TYPICAL RDS(on) = 4
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Sy mb o l
P a ramet er
VDS Drain-source Voltage (VGS = 0)
V DGR
VGS
ID
ID
Drain- gate Voltage (RGS = 20 k)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
IDM () Drain Current (pulsed)
Ptot T otal Dissipation at Tc = 25 oC
Derating Factor
dv/dt(1) Peak Diode Recovery voltage slope
VISO Insulation Withstand Voltage (DC)
Ts tg Storage Temperat ure
Tj Max. Operating Junction T emperature
() Pulse width limited by safe operating area
(*) Limited only by maximum temperature allowed
October 1999
Va l u e
Un it
STP4NB100 ST P4NB100F P
1000
V
1000
V
± 30
V
3.8
3.8(*)
A
2.4
2.4(*)
A
15.2
15.2
A
125 40 W
1
0.32
W /o C
4 4 V/ns
2000
-65 to 150
150
( 1) ISD 3.8A, di/dt 200 A/µs, VDD V(BR)DSS, Tj TJMAX
V
oC
oC
1/9






P4NB100 Datasheet, Funktion
www.DataSheet4U.com
STP4NB100/STP4NB100FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9

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