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GM71VS16163CL Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer GM71VS16163CL
Beschreibung (GM71VS16163CL / GM71V16163C) 1M x 16-Bit CMOS DRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 13 Seiten
GM71VS16163CL Datasheet, Funktion
GM71V16163C
GM71VS16163CL
1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
Description
The GM71V(S)16163C/CL is the new generation
dynamic RAM organized 1,048,576 x 16 bit.
GM71V(S)16163C/CL has realized higher density,
higher performance and various functions by utilizing
advanced CMOS process technology. The
GM71V(S)16163C/CL offers Extended Data
out(EDO) Mode as a high speed access mode.
Multplexed address inputs permit the
GM71V(S)16163C/CL to be packaged in standard
400 mil 42pin plastic SOJ, and standard 400mil
44(50)pin plastic TSOP II. The package size provides
high system bit densities and is compatible with
widely available automated testing and insertion
equipment.
Pin Configuration
Features
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time (Unit: ns)
t t t tRAC CAC RC
HPC
GM71V(S)16163C/CL-5 50 13 84 20
GM71V(S)16163C/CL-6 60 15 104 25
GM71V(S)16163C/CL-7 70 18 124 30
GM71V(S)16163C/CL-8 80 20 144 35
* Low Power
Active : 396/360/324/288mW (MAX)
Standby : 7.2mW (MAX)
0.83mW (L-series : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/64ms
* 4096 Refresh Cycles/128ms (L-series)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-series)
* 2 CAS byte Control
42 SOJ
44(50) TSOP II
VCC 1
42 VSS
I/O0 2
41 I/O15
I/O1 3
40 I/O14
I/O2 4
39 I/O13
I/O3 5
38 I/O12
VCC 6
37 VSS
I/O4 7
36 I/O11
I/O5 8
35 I/O10
I/O6 9
34 I/O9
I/O7 10
33 I/O8
NC 11
32 NC
NC 12
31 LCAS
WE 13
30 UCAS
RAS 14
29 OE
A11 15
A10 16
mA0 17
oA1 18
.cA2 19
A3 20
uVCC 21
www.datasheet4Rev 0.1 / Apr’01
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
(Top View)
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 15
NC 16
WE 17
RAS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
50 VSS
49 I/O15
48 I/O14
47 I/O13
46 I/O12
45 VSS
44 I/O11
43 I/O10
42 I/O9
41 I/O8
40 NC
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS






GM71VS16163CL Datasheet, Funktion
Read Cycle
Symbol
Parameter
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Address
tOEA Access Time from OE
tRCS Read Command Setup Time
tRCH Read Command Hold Time to CAS
tRRH Read Command Hold Time to RAS
tRAL Column Address to RAS Lead Time
tCAL Column Address to CAS Lead Time
tCLZ CAS to Output in Low-Z
tOH Output Data Hold Time
tOHO Output Data Hold Time from OE
tOFF Output Buffer Turn-off Time
tOEZ Output Buffer Turn-off Time to OE
tCDD CAS to DIN Delay Time
tRCHR Read Command Hold Time from RAS
tOHR Output Data hold Time from RAS
tOFR Output Buffer turn off to RAS
tWEZ Output Buffer turn off to WE
tWED WE to DIN Deray Time
tROD RAS to DIN Delay Time
GM71V16163C
GM71VS16163CL
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5
C/CL-6
C/CL-7
C/CL-8
Unit Note
Min Max Min Max Min Max Min Max
- 50 - 60 - 70 - 80 ns 8,9
- 13 - 15 - 18 - 20 ns 9,10,17
- 25 - 30 - 35 - 40 ns 9,11,17
- 13 - 15 - 18 - 20 ns 9
0-
0-
0-
0-
0-
0-
0 - ns 21
0 - ns 12,22
5 - 5 - 5 - 5 - ns 12
25 - 30 - 35 - 40 - ns
15 - 18 - 23 - 28 - ns
0 - 0 - 0 - 0 - ns
3 - 3 - 3 - 3 - ns 27
3 - 3 - 3 - 3 - ns
- 13 - 15 - 15 - 15 ns 13,27
- 13 - 15 - 15 - 15 ns 13
13 - 15 - 18 - 20 - ns 5
50 - 60 - 70 - 80 - ns
3- 3-
3-
3 - ns 27
- 13 - 15 - 15 - 15 ns 27
- 13 - 15 - 15 - 15 ns
13 - 15 - 18 - 20 - ns
13 - 15 - 18 - 20 - ns
Rev 0.1 / Apr’01

6 Page









GM71VS16163CL pdf, datenblatt
Notes concerning 2CAS control
GM71V16163C
GM71VS16163CL
Please do not separate the UCAS / LCAS operation timing intentionally. However skew between
UCAS / LCAS are allowed under the following conditions.
1. Each of the UCAS / LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed;such as following.
RAS
UCAS
LCAS
WE
Delayed write
Early write
3. Closely separated upper/lower byte control is not allowed. However when the condition
(tcp < tUL)is satisfied,EDO page mode can be performed.
RAS
UCAS
LCAS
tUL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
Rev 0.1 / Apr’01

12 Page





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