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GM71VS18160CL Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer GM71VS18160CL
Beschreibung (GM71VS18160CL / GM71VS18160C) 1M x 16-Bit CMOS DRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 10 Seiten
GM71VS18160CL Datasheet, Funktion
GM71V18160C
GM71VS18160CL
1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
Description
The GM71V(S)18160C/CL is the new
generation dynamic RAM organized 1,048,576
x 16 bit. GM71V(S)18160C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71V(S)18160C/CL offers
Fast Page Mode as a high speed access mode.
Multiplexed address inputs permit the
GM71V(S)18160C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and
standard 400mil 44(50)pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
Pin Configuration
Features
* 1,048,576 Words x 16 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (3V+/-0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
t tRAC CAC tRC tPC
GM71V(S)18160C/CL-5
GM71V(S)18160C/CL-6
GM71V(S)18160C/CL-7
50 13 90 35
60 15 110 40
70 18 130 45
* Low Power
Active : 684/612/540/468mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.54mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control
42 SOJ
44(50) TSOP II
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 12
WE 13
RAS 14
NC 15
NC 16
mA0 17
oA1 18
.cA2 19
A3 20
uVCC 21
www.datasheet4Rev 0.1 / Apr’01
42 VSS
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 VSS
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
(Top View)
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 15
NC 16
WE 17
RAS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
50 VSS
49 I/O15
48 I/O14
47 I/O13
46 I/O12
45 VSS
44 I/O11
43 I/O10
42 I/O9
41 I/O8
40 NC
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS






GM71VS18160CL Datasheet, Funktion
Read Cycle
Symbol
Parameter
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Address
tOAC Access Time from OE
tRCS Read Command Setup Time
tRCH Read Command Hold Time to CAS
tRRH Read Command Hold Time to RAS
tRAL Column Address to RAS Lead Time
tCAL Column Address to CAS Lead Time
tCLZ CAS to Output in Low-Z
tOH Output Data Hold Time
tOHO Output Data Hold Time from OE
tOFF Output Buffer Turn-off Time
tOEZ Output Buffer Turn-off Time to OE
tCDD CAS to DIN Delay Time
GM71V18160C
GM71VS18160CL
GM71V(S)18160 GM71V(S)18160 GM71V(S)18160
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
Note
- 50 - 60 - 70 ns 8,9
- 13 - 15 - 18
ns 9,10,17
- 25 - 30 - 35
ns 9,10,17
- 13 - 15 - 18 ns 9,25
0- 0- 0-
ns
0- 0- 0-
ns 12,22
5 - 5 - 5 - ns 12
25 - 30 - 35 -
ns
25 - 30 - 35 -
ns
0- 0- 0-
ns
3- 3- 3-
ns
3- 3- 3-
ns
- 13 - 15 - 15
ns
13
- 13 - 15 - 15
ns
13
13 - 15 - 18 -
ns
5
Write Cycle
Symbol
Parameter
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tD
H
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
GM71V(S)18160 GM71V(S)18160 GM71V(S)18160
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
0-
0 - 0-
ns
8 - 10 - 15 -
ns
8 - 10 - 10 -
ns
13 - 15 - 18 -
ns
13 - 15 - 18 -
ns
0-
0 - 0-
ns
8 - 10 - 15 -
ns
Note
14,21
21
23
15,23
15,23
Rev 0.1 / Apr’01

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