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GM71VS17800CL Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer GM71VS17800CL
Beschreibung (GM71VS17800CL / GM71V17800C) 2M x 8-Bit CMOS DRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 9 Seiten
GM71VS17800CL Datasheet, Funktion
Description
The GM71V(S)17800C/CL is the new
generation dynamic RAM organized 2,097,152
x 8 bit. GM71V(S)17800C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71V(S)17800C/CL offers
Fast Page Mode as a high speed access mode.
Multiplexed address inputs permit the
GM71V(S)17800C/CL to be packaged in
standard 400 mil 28pin plastic SOJ, and
standard 400mil 28pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
Pin Configuration
GM71V17800C
GM71VS17800CL
2,097,152 WORDS x 8 BIT
CMOS DYNAMIC RAM
Features
* 2,097,152 Words x 8 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
t tRAC CAC tRC tPC
GM71V(S)17800C/CL-5
GM71V(S)17800C/CL-6
GM71V(S)17800C/CL-7
50 13 90 35
60 15 110 40
70 18 130 45
* Low Power
Active : 468/432/396mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.54mW (L- version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L- version)
28 SOJ
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
WE 6
RAS 7
NC 8
A10 9
A0 10
A1 11
A2 12
A3 13
mVCC 14
www.datasheet4u.coRev 0.1 / Apr’01
28 VSS
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
28 TSOP II
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
WE 6
RAS 7
NC 8
A10 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28 VSS
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
(Top View)






GM71VS17800CL Datasheet, Funktion
Read- Modify-Write Cycle
Symbol
Parameter
tRWC
tRWD
tCWD
tAWD
tOEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
OE Hold Time from WE
GM71V17800C
GM71VS17800CL
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
131 - 155 - 181 -
ns
73 - 85 - 98 -
ns
36 - 40 - 46 -
ns
48 - 55 - 63 -
ns
13 - 15 - 18 -
ns
Note
14
14
14
Refresh Cycle
Symbol
Parameter
tCSR CAS Setup Time
(CAS-before-RAS Refresh Cycle)
tCHR CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tWRP WE Setup Time
(CAS-before-RAS Refresh Cycle)
tWRH WE Hold Time
(CAS-before-RAS Refresh Cycle)
tRPC RAS Precharge to CAS Hold Time
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
Note
5 - 5 - 5 - ns
8 - 10 - 10 - ns
0 - 0 - 0 - ns
10 - 10 - 10 -
5- 5- 5-
ns
ns
Fast Page Mode Cycle
Symbol
Parameter
tPC
tRASP
tACP
tRHCP
Fast Page Mode Cycle Time
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
35 - 40 - 45 - ns
- 100,000 - 100,000 - 100,000 ns
- 30 - 35 - 40 ns
30 - 35 - 40 - ns
Note
16
9,17
Rev 0.1 / Apr’01

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