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GM71V65803A Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer GM71V65803A
Beschreibung (GM71VS65803AL / GM71V65803A) 8M x 8-Bit CMOS DRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 25 Seiten
GM71V65803A Datasheet, Funktion
LG Semicon Co.,Ltd.
GM71V65803A
GM71VS65803AL
8,388,608 WORDS x 8 BIT
CMOS DYNAMIC RAM
Description
Pin Configuration
The GM71V(S)65803A/AL is the new generation
dynamic RAM organized 8,388,608 words by 8bits.
The GM71V(S)65803A/AL utilizes advanced CMOS
Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
The GM71V(S)65803A/AL offers Extended Data
Out (EDO) Mode as a high speed access mode.
Features
* 8,388,608 Words x 8 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC tAA tCAC tRC
tHPC
GM71V(S)65803A/AL-5 50 25 13 84 20
GM71V(S)65803A/AL-6 60 30 15 104 25
32 SOJ / TSOP II
VCC 1
IO0 2
IO1 3
IO2 4
IO3 5
NC 6
VCC 7
/WE 8
/RAS 9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
32 VSS
31 IO7
30 IO6
29 IO5
28 IO4
27 VSS
26 /CAS
25 /OE
24 NC
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
*Power dissipation
- Active : 702mW/630mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
4096 cycles/64 §Â (GM71V65803A)
4096 cycles/128§Â (GM71VS65803AL)(L_Version)
*CBR & Hidden Refresh
4096 cycles/64 §Â (GM71V65803A)
m4096 cycles/128 §Â (GM71VS65803AL)( L-Version )
o*4 variations of refresh
.c-RAS-only refresh
u-CAS-before-RAS refresh
t4-Hidden refresh
-Self refresh (L-Version)
ee*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
www.datash*Battery Back Up Operation ( L-Version )
(Top View)
1






GM71V65803A Datasheet, Funktion
LG Semicon
GM71V(S)65803A/AL
Write Cycles
Symbol
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
Parameter
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
Data-in Hold Time
GM71V(S)65803A/AL-5 GM71V(S)65803A/AL-6
Min Max Min
Max
0-0
-
8 - 10 -
8 - 10 -
13 - 17
-
8 - 10 -
0-0
-
8 - 10 -
Unit Notes
§À 14
§À
§À
§À
§À
§À 15
§À 15
Read-Modify-Write Cycles
Symbol
Parameter
GM71V(S)65803A/AL-5 GM71V(S)65803A/AL-6
Min
Max Min
Max
Unit Notes
tRWC Read-Modify-Write Cycle Time
116
-
140
- §À
tRWD RAS to WE Delay Time
67 - 79 - §À 14
tCWD CAS to WE Delay Time
30 - 34 - §À 14
tAWD Column Address to WE Delay Time
42
-
49
- §À 14
tOEH OE Hold Time from WE
13 - 15 - §À
Refresh Cycles
Symbol
Parameter
tCSR
tCHR
tWRP
tWRH
tRPC
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
WE setup time
(CAS-before-RAS Refresh Cycle)
WE hold time
(CAS-before-RAS Refresh Cycle)
RAS Precharge to CAS Hold Time
GM71V(S)65803A/AL-5
Min Max
GM71V(S)65803A/AL-6
Min Max
Unit
Notes
5- 5
- §À
8 - 10 - §À
0- 0
- §À
8 - 10 - §À
5- 5
- §À
6

6 Page









GM71V65803A pdf, datenblatt
LG Semicon
GM71V(S)65803A/AL
RAS
CAS
ADDRESS
WE
DIN
OE
DOUT
tRC
tRAS
tRP
tT
tRCD
tRSH
tCAS
tCRP
tCSH
tASR
tRAH
ROW
tASC
tCAH
COLUMN
tRCS
tCWL
tRWL
tWP
tDZC
tDS tDH
tDZO
High-Z
DIN
tODD
tOEP
tOEH
High-Z
tOEZ
tCLZ
INVALID
OUTPUT
*18
FIGURE 3. DELAYED WRITE CYCLE
12

12 Page





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