PDF GM71VS65403AL Data sheet ( Hoja de datos )

Número de pieza	GM71VS65403AL
Descripción	(GM71VS65403AL / GM71V65403A) 16M x 4-Bit CMOS DRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! LG Semicon Co.,Ltd. GM71V65403A GM71VS65403AL 16,777,216 WORDS x 4 BIT CMOS DYNAMIC RAM Description Pin Configuration The GM71V(S)65403A/AL is the new generation dynamic RAM organized 16,777,216 words by 4bits. The GM71V(S)65403A/AL utilizes advanced CMOS Silicon Gate Process Technology as well as advanced circuit techniques for wide operating margins, both internally and to the system user. System oriented features include single power supply of 3.3V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The GM71V(S)65403A/AL offers Extended Data Out(EDO) Mode as a high speed access mode. Features * 16,777,216 Words x 4 Bit * Extended Data Out (EDO) Mode Capability * Fast Access Time & Cycle Time (Unit: ns) tRAC tAA tCAC tRC tHPC GM71V(S)65403A/AL-5 50 25 13 84 20 GM71V(S)65403A/AL-6 60 30 15 104 25 32 SOJ / TSOP II VCC 1 IO0 2 IO1 3 NC 4 NC 5 NC 6 VCC 7 /WE 8 /RAS 9 A0 10 A1 11 A2 12 A3 13 A4 14 A5 15 VCC 16 32 VSS 31 IO3 30 IO2 29 NC 28 NC 27 VSS 26 /CAS 25 /OE 24 NC 23 A11 22 A10 21 A9 20 A8 19 A7 18 A6 17 VSS Power dissipation - Active : 684mW/612mW(MAX) - Standby : 1.8 mW ( CMOS level : MAX ) 0.54mW ( L-Version : MAX) EDO page mode capability Access time : 50ns/60ns (max) Refresh cycles - RAS only Refresh 4096 cycles/64 §Â (GM71V65403A) 4096 cycles/128§Â (GM71VS65403AL)(L_Version) CBR & Hidden Refresh 4096 cycles/64 §Â (GM71V65403A) m4096 cycles/128 §Â (GM71VS65403AL)( L-Version ) o4 variations of refresh .c-RAS-only refresh u-CAS-before-RAS refresh t4-Hidden refresh -Self refresh (L-Version) eeSingle Power Supply of 3.3V+/-10 % with a built-in VBB generator www.datashBattery Back Up Operation ( L-Version ) (Top View) 1 1 page LG Semicon GM71V(S)65403A/AL Read Cycles Symbol Parameter tRAC Access Time from RAS tCAC Access Time from CAS tAA Access Time from Column Address tOAC Access Time from OE tRCS Read Command Set-up Time tRCH Read Command Hold Time to CAS tRRH Read Command Hold Time to RAS tRAL Column Address to RAS Lead Time tCAL Column Address to CAS Lead Time tOFF Output Buffer Turn-off Delay Time from CAS tOEZ Output Buffer Turn-off Delay Time from OE tCDD CAS to DIN Delay Time tRDD RAS to DIN Delay Time tWDD tOFR tWEZ WE to DIN Delay Time Output Buffer Turn-off Delay Time from RAS Output Buffer Turn-off Delay Time from WE tOH Output Data Hold Time tOHR Output Data Hold Time from RAS tRCHR Read Command Hold Time from RAS tOHO Output data hold time from OE tCLZ CAS to Output in Low - Z GM71V(S)65403A/AL-5GM71V(S)65403A/AL-6 Unit Min Max Min Max Notes - 50 - 60 §À 8,9 - 13 - 15 §À 9,10,17 - 25 - 30 §À 9,11,17 - 13 - 15 §À 9 0 - 0 - §À 0 - 0 - §À 12 0 - 0 - §À 12 25 - 30 - §À 15 - 18 - §À - 13 - 15 §À 13,21 - 13 - 15 §À 13 13 - 15 - §À 5 13 - 15 - §À 13 - 15 - §À - 13 - 15 §À 13,21 - 13 - 15 §À 13 3 - 3 - §À 21 3 - 3 - §À 21 50 - 60 - §À 3 - 3 - §À 0 - 0 - §À 5 5 Page LG Semicon GM71V(S)65403A/AL RAS CAS ADDRESS WE DIN DOUT tRC tRAS tRP tRSH tT tRCD tCAS tCRP tCSH tASR tRAH ROW tASC tCAH COLUMN tWCS tWCH tDS DIN tDH High-Z FIGURE 2. EARLY WRITE CYCLE 11 11 Page

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