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GS8330DW72 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8330DW72
Beschreibung (GS8330DW36/72) 36M Double Late Write SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8330DW72 Datasheet, Funktion
Preliminary
GS8330DW36/72C-250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Σ36Mb
1x1Dp CMOS I/O
200 MHz–250 MHz
1.8 V VDD
Double Late Write SigmaRAM™
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 72Mb and 144Mb devices
Key Fast Bin Specs
Cycle Time
Symbol
tKHKH
-250
4.0 ns
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Access Time
tKHQV
2.1 ns
Functional Description
SigmaRAM Family Overview
Because SigmaRAMs are synchronous devices, address data
GS8330DW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 37,748,736-bit (36Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
ΣRAMs are offered in a number of configurations including
Deselect (DCD) output deselect protocol.
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
mthe task at hand.
tasheet4u.coRev: 1.00 6/2003
1/30
© 2003, GSI Technology, Inc.
www.daSpecifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.






GS8330DW72 Datasheet, Funktion
Preliminary
GS8330DW36/72C-250/200
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline
mode NBT SRAMs.
SigmaRAM Double Late Write with Pipelined Read
Read
W rite
Read
W rite
Read
CK
Address
A
B
C
D
E
F
ADV
/E1
/W
DQ QA DB QC DD
CQ
Key
Hi-Z
Access
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
Read
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
W Ba Bb Bc Bd
HX X X X
LL H H H
LH L H H
LH H L H
LH H H L
LL L L L
LH H H H
Rev: 1.00 6/2003
6/30
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

6 Page









GS8330DW72 pdf, datenblatt
.
CK
Address
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
CQ
Bank 1
Read
A
Preliminary
GS8330DW36/72C-250/200
Pipelined Read Bank Switch with E1 Deselect
No Op
Read
Read
Read
XX C D E F
QA
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
QC
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
CMOS Output Driver Impedance Control
CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between
SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point
applications.
Rev: 1.00 6/2003
12/30
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

12 Page





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