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GS8320Z36T Schematic ( PDF Datasheet ) - ETC

Teilenummer GS8320Z36T
Beschreibung (GS8320Z18T/36T) 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Hersteller ETC
Logo ETC Logo 




Gesamt 25 Seiten
GS8320Z36T Datasheet, Funktion
100-Pin TQFP
Commercial Temp
Industrial Temp
Product Preview
GS8320Z18/36T-250/225/200/166/150/133
36Mb Pipelined and Flow Through 250 MHz133 MHz
Synchronous NBT SRAM
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
Functional Description
• NBT (No Bus Turn Around) functionality allows zero wait
The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
read-write-read bus utilization; Fully pin-compatible with
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
both pipelined and flow through NtRAM™, NoBL™ and
pipelined read/double late write or flow through read/single
ZBT™ SRAMs
late write SRAMs, allow utilization of all available bus
• 2.5 V or 3.3 V +10%/5% core power supply
bandwidth by eliminating the need to insert deselect cycles
• 2.5 V or 3.3 V I/O supply
when the device is switched from read to write cycles.
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.3 2.5 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3.3 V
Curr (x18) 365 335 300 265 240 220 mA
Curr (x32/x36) 430 390 350 305 280 245 mA
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36T may be configured by the user to operate
2.5 V
Curr (x18) 360 330 295 260 235 215 mA
Curr (x32/x36) 420 380 340 295 270 235 mA
Flow
Through
2-1-1-1
tKQ
tCycle
6.0 6.5 7.5 8.5 10 11 ns
7.0 7.5 8.5 10 10 15 ns
3.3 V
Curr (x18) 200 200 180 180 180 135 mA
Curr (x32/x36) 230 230 195 195 195 145 mA
2.5 V
Curr (x18) 200 200 180 180 180 130 mA
Curr (x32/x36) 225 225 195 195 195 145 mA
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
BC
DE
F
Read/Write
R
WR
W
R
W
Flow Through
Data I/O
Pipelined
Data I/O
QA DB QC DD QE
QA DB QC DD QE
Rev: 1.01 10/2001
1/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.






GS8320Z36T Datasheet, Funktion
Product Preview
GS8320Z18/36T-250/225/200/166/150/133
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W BA BB BC BD
HX X X X
LL H H H
LH L H H
LH H L H
LH H H L
LL L L L
LH H H H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.01 10/2001
6/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

6 Page









GS8320Z36T pdf, datenblatt
Product Preview
GS8320Z18/36T-250/225/200/166/150/133
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS8320Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS8321Z18/36
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked VDD or VDDQ
on pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode
applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By
using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT
SRAMs (GS8321Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active
low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
Rev: 1.01 10/2001
12/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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