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PDF GL811E Data sheet ( Hoja de datos )
| Número de pieza | GL811E | |
| Descripción | USB 2.0 to ATA / ATAPI Bridge Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de GL811E (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Genesys Logic, Inc.
GL811E
USB 2.0 to ATA / ATAPI
Bridge Controller
Datasheet
Revision 1.22
Dec. 29, 2004
1 page  
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
LIST OF FIGURES
FIGURE 3.1 - 48 PIN LQFP/TQFP PINOUT DIAGRAM .......................................................... 9
FIGURE 3.2 - 64 PIN LQFP/TQFP PINOUT DIAGRAM ........................................................ 10
FIGURE 4.1 - BLOCK DIAGRAM ............................................................................................. 13
FIGURE 6.1 - INITIATING A MULTIWORD DMA DATA BURST ........................................... 20
FIGURE 6.2 - SUSTAINING A MULTIWORD DMA DATA BURST.......................................... 21
FIGURE 6.3 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST........................ 21
FIGURE 6.4 - HOST TERMINATING A MULTIWORD DMA DATA BURST ............................ 22
FIGURE 6.5 - INITIATING AN ULTRA DMA DATA-IN BURST .............................................. 24
FIGURE 6.6 - SUSTAINED ULTRA DMA DATA-IN BURST .................................................... 24
FIGURE 6.7 - HOST PAUSING AN ULTRA DMA DATA-IN BURST........................................ 25
FIGURE 6.8 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST .......................... 25
FIGURE 6.9 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST .............................. 26
FIGURE 6.10 - INITIATING AN ULTRA DMA DATA-OUT BURST ........................................ 27
FIGURE 6.11 - SUSTAINED ULTRA DMA DATA-OUT BURST.............................................. 27
FIGURE 6.12 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST .............................. 28
FIGURE 6.13 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST........................... 29
FIGURE 6.14 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST..................... 30
FIGURE 7.1 - GL811E 48 PIN LQFP PACKAGE................................................................... 31
FIGURE 7.2 - GL811E 48 PIN TQFP PACKAGE................................................................... 32
FIGURE 7.3 - GL811E 64 PIN LQFP PACKAGE................................................................... 33
FIGURE 7.4 - GL811E 64 PIN TQFP PACKAGE................................................................... 34
© 2000-2004 Genesys Logic Inc. - All rights reserved.
Page 5
5 Page 
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
3.2 Pin Descriptions
Table 3.1 - Pin Descriptions
Pin Name
GPIO7
GPIO5~6
IODD[8:11]
DVCC1~2
48Pin#
1
-
2~5
6,43
64 Pin# I/O Type
1
B
(tri)
GPIO7 (**)
3,4 O AP programmable
5~8
B
(tri)
IDE data bus 8~11
56,9 P Digital VCC
Description
DGND1~2
7,42
IODD[12:15] 8~11
CBLID_
12
CS1_
13
DA2/SK
14
RESET#
RPU
15
16
55,10
11~14
15
20
-
22
23
P Digital ground
B
(tri)
IDE data bus 12~15
I
(tri)
Cable select input
O
(tri)
Chip select 1
O
(tri)
IDE address 2 / Serial data clock for EEPROM
I
(pu)
Reset pin (***)
A 3.3v output
AVCC0~1
17,24 24,31
P Analog VCC
DPF
18 25
B Full speed DP
DPH
19 26
B High speed DP
DMF
20 27
B Full speed DM
DMH
21 28
B High speed DM
AGND0~1 22,27 29,34
P Analog ground
RREF
23 30
A Reference resister connect (****)
X2
25 32
B Crystal output
X1
TEST
CS0_
DA0~1
DA2
INTRQ
DMACK_
IORDY
26
28
29
30,31
-
32
33
34
33
-
37
38,39
21
44
45
46
I Crystal input, 12Mhz
I
(pd)
TEST mode input
O
(tri)
Chip select 0
O
(tri)
IDE address 0~1
O
(tri)
IDE address 2
I
(tri)
IDE interrupt input
O
(tri)
IDE acknowledge
I
(pu)
IDE ready
© 2000-2004 Genesys Logic Inc. - All rights reserved.
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GL811E.PDF ] | |
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