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PDF DP8573A Data sheet ( Hoja de datos )
| Número de pieza | DP8573A | |
| Descripción | Real Time Clock (RTC) | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 1993
DP8573A Real Time Clock (RTC)
General Description
The DP8573A is intended for use in microprocessor based
systems where information is required for multi-tasking data
logging or general time of day date information This device
is implemented in low voltage silicon gate microCMOS tech-
nology to provide low standby power in battery back-up en-
vironments The circuit’s architecture is such that it looks
like a contiguous block of memory or I O ports organized as
one block of 32 bytes This includes the Control Registers
the Clock Counters the Alarm Compare RAM and the Time
Save RAM
Time and date are maintained from 1 100 of a second to
year and leap year in a BCD format 12 or 24 hour modes
Day of week and day of month counters are provided Time
is controlled by an on-chip crystal oscillator requiring only
the addition of the 32 768 kHz crystal and two capacitors
Power failure logic and control functions have been integrat-
ed on chip This logic is used by the RTC to issue a power
fail interrupt and lock out the mP interface The time power
fails may be logged into RAM automatically when VBB l
VCC Additionally two supply pins are provided When VBB
l VCC internal circuitry will automatically switch from the
main supply to the battery supply
The DP8573A’s interrupt structure provides three basic
types of interrupts Periodic Alarm Compare and Power
Fail Interrupt mask and status registers enable the masking
and easy determination of each interrupt
Features
Y Full function real time clock calendar
12 24 hour mode timekeeping
Day of week counter
Parallel resonant oscillator
Y Power fail features
Internal power supply switch to external battery
Power Supply Bus glitch protection
Automatic log of time into RAM at power failure
Y On-chip interrupt structure
Periodic alarm and power fail interrupts
Block Diagram
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9981
TL F 9981 – 1
RRD-B30M75 Printed in U S A
1 page  
Connection Diagrams
Dual-In-Line
Plastic Chip Carrier
Top View
Order Number DP8573AN
See NS Package Number N24C
TL F 9981 – 5
Functional Description
The DP8573A contains a fast access real time clock inter-
rupt control logic and power fail detect logic All functions of
the RTC are controlled by a set of seven registers A simpli-
fied block diagram that shows the major functional blocks is
given in Figure 1
The blocks are described in the following sections
1 Real Time Clock
2 Oscillator Prescaler
3 Interrupt Logic
4 Power Failure Logic
5 Additional Supply Management
The memory map of the RTC is shown in the memory ad-
dressing table (Figure 2) A control bit in the Main Status
Register is used to select either control register block
INITIAL POWER-ON of BOTH VBB and VCC
VBB and VCC may be applied in any sequence In order for
the power fail circuitry to function correctly whenever power
is off the VCC pin must see a path to ground through a
maximum of 1 MX The user should be aware that the con-
trol registers will contain random data The user should en-
sure that the RTC is not in test mode (see register descrip-
tions)
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2 the clock has 8 bytes of counters
which count from 1 100 of a second to years Each counter
counts in BCD and is synchronously clocked The count se-
quence of the individual byte counters within the clock is
shown later in Table VII Note that the day of week day of
month and month counters all roll over to 1 The hours
counter in 12 hour mode rolls over to 1 and the AM PM bit
toggles when the hours rolls over to 12 (AM e 0 PM e 1)
The AM PM bit is bit D7 in the hours counter
All other counters roll over to 0 Upon initial application of
power the counters will contain random information
5
Top View
Order Number DP8573AV
See NS Package Number V28A
TL F 9981 – 6
TL F 9981 – 7
FIGURE 2 DP8573A Internal Memory Map
5 Page 
Functional Description (Continued)
MAIN STATUS REGISTER
TL F 9981 – 12
The Main Status Register is always located at address 0
regardless of the register block selected
D0 This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt) This is unlike D3
which can be set by an internal event but may not cause an
interrupt This bit is reset when the interrupt status bits in the
Main Status Register are cleared
D1 – D3 These three bits of the Main Status Register are the
main interrupt status bits Any bit may be a one when any of
the interrupts are pending Once an interrupt is asserted the
mP will read this register to determine the cause These
interrupt status bits are not reset when read Except for D1
to reset an interrupt a one is written back to the correspond-
ing bit that is being tested D1 is reset whenever the PFAIL
pin e logic 1 This prevents loss of interrupt status when
reading the register in a polled mode D1 and D3 are set
regardless of whether these interrupts are masked or not by
bits D6 and D7 of Interrupt Control Registers 0 and 1
D4 D5 and D7 General purpose RAM bits
D6 Bit D6 controls the register block to be accessed (see
memory map)
PERIODIC FLAG REGISTER
backed mode Bit D6 is automatically set to 1 on initial pow-
er-up or an oscillator fail event The oscillator fail flag is
reset by writing a one to the clock start stop bit in the Real
Time Mode Register with the crystal oscillating
When D6 is written to it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application When set to a one this bit configures the TCP
for single power supply applications This bit is automatically
set on initial power-up or an oscillator fail event When set
D6 disables the oscillator reference circuit The result is that
the oscillator is referenced to VCC When a zero is written to
D6 the oscillator reference is enabled thus the oscillator is
referenced to VBB This allows operation in standard battery
standby applications
At initial power on if the DP8573A is going to be pro-
grammed for battery backed mode the VBB pin should be
connected to a potential in the range of 2 2V to VCC b
0 4V
For single supply mode operation the VBB pin should be
connected to GND and the PFAIL pin connected to VCC
D7 Writing a one to this bit enables the test mode register
at location 1F (see Table III) This bit should be forced to
zero during initialization for normal operation If the test
mode has been entered clear the test mode register before
leaving test mode (See separate test mode application
note for further details )
TIME SAVE CONTROL REGISTER
TL F 9981 – 13
The Periodic Flag Register has the same bit for bit corre-
spondence as Interrupt Control Register 0 except for D6
and D7 For normal operation (i e not a single supply appli-
cation) this register must be written to on initial power up or
after an oscillator fail event D0–D5 are read only bits D6
and D7 are read write
D0 – D5 These bits are set by the real time rollover events
(Time Change e 1) The bits are reset when the register is
read and can be used as selective data change flags
D6 This bit performs a dual function When this bit is read a
one indicates that an oscillator failure has occurred and the
time information may have been lost Some of the ways an
oscillator failure might be caused are failure of the crystal
shorting OSC IN or OSC OUT to GND or VCC removal of
crystal removal of battery when in the battery backed mode
(when a ‘‘0’’ is written to D6) lowering the voltage at the
VBB pin to a value less than 2 2V when in the battery
TL F 9981 – 14
D0 – D5 General purpose RAM bits
D6 Not Available appears as logic 0 when read
D7 Time Save Enable bit controls the loading of real-time-
clock data into the Time Save RAM When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers and when a zero is written to this bit the time
in the Time Save RAM is frozen This eliminates any syn-
chronization problems when reading the clock thus negat-
ing the need to check for a counter rollover during a read
cycle
This bit must be set to a one prior to power failing to enable
the Time Save feature When the power fails this bit is auto-
matically reset and the time is saved in the Time Save RAM
REAL TIME MODE REGISTER
TL F 9981 – 15
11
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| PDF Descargar | [ Datasheet DP8573A.PDF ] | |
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