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ADD8502 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADD8502
Beschreibung Integrated LCD Grayscale Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADD8502 Datasheet, Funktion
a
Integrated LCD
Grayscale Generator
ADD8502
FEATURES
Two Mask Programmable Sets of Five Reference Levels
Dual 10-Bit DACs for Flicker Offset and Range Adjustment
Integrated VCOM Switching
Single-Supply Operation: 5.0 V
Low Supply Current: 300 A
Global Power Save Mode: 1 A Max
Fast Settling Time for Load Change: 20 s
Stable with 20 nF/100 Loads
CMOS/TTL Input Levels
APPLICATIONS
Color TFT Cell Phones
Color TFT PDAs
GENERAL DESCRIPTION
The ADD8502 is an integrated, high accuracy, programmable
grayscale generator. Two sets of five output reference voltages
are mask programmed to 0.2% resolution. The outputs switch
between the two sets of five levels. The reference levels are selected
from a 512 tap resistor network using a via mask.
ADD8502 includes two serially addressable, 10-bit digital-to-
analog converters (DACs) and five fast, low current buffers.
The dual DACs set the endpoint voltages applied to the resistor
network to adjust for flicker and range. The two power save modes
can reduce the total current to less than 1 µA and feature fast
recovery time from Shutdown/Sleep Mode. The ADD8502
accepts CMOS or TTL inputs for all controls, including the
common drive circuit levels.
ADD8502 operates over the industrial temperature range from
–40°C to +85°C and is available in a space-saving 24-lead
4 mm ϫ 4 mm frame chip scale package.
FUNCTIONAL BLOCK DIAGRAM
REV2
VDD
VREF+
VDD/2
10-BIT
DAC A
VREF–
VL
VP0
VN0
R
R VP0
R
VN4
A0
A1
SCK
DIN
CS-LD
DIGITAL
CORE
POWER
SAVE
LOGIC
PSK
GS1
GS2
VDD/2
VREF+
10-BIT
DAC B
VREF–
MUX
VP4
VN4
R
VP4
R
VN0
R
R
VDD
A2
A3
A4
VCOM
LOGIC
VDD
GND
V0
V1
V2
V3
V4
COM
COM_M
REV1 CM CV4
sheet4u.comREV. 0
taInformation furnished by Analog Devices is believed to be accurate and
areliable. However, no responsibility is assumed by Analog Devices for its
.duse, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or
wwwotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






ADD8502 Datasheet, Funktion
ADD8502
Pin No. Mnemonic Name
I/O Description
21 REV2 Reference Output I When PSK is HIGH and GS1 or GS2 is LOW, then INVERT selects the output
Select
levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to
reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4
are connected to reference levels VN0 to VN4, respectively. When PSK is HIGH
and GS1 and GS2 are HIGH, V1–V3 are, Hi-Z state, but V0 and V4 are still
connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0
and V4 switch to VN0 and VN4 when REV is LOW.
22 GS2
Sleep Mode
I When GS1 and GS2 are HIGH, the middle three output buffers are shut down
Select
and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2
leave the outputs of A1 to A3 fully active.
23 GS1
Sleep Mode
I When GS1 and GS2 are HIGH, the middle three output buffers are shut down
Select
and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the
24 PSK
Global Power
outputs of A1 to A3 fully active.
I When PSK is pulled LOW, the chip will be put into the full Power-Down Mode.
Shutdown
The DACs, resistor ladder network preamps, and output buffers will all be shut
down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to
normal operation is within 30 µs.
All digital inputs accept CMOS or TTL logic levels.
–6– REV. 0

6 Page









ADD8502 pdf, datenblatt
ADD8502
Control Code
C3 C2 C1 C0
0 000
0 001
0 010
0 011
0 100
0 101
0 110
0 111
1 000
1 001
1 010
1 011
1 100
1 101
1 110
1 111
Status
No Change
Load DAC A
Load DAC B
No Change
Load DAC A
Load DAC B
No Change
No Change
Load DACs
A, B with Same
10-Bit Code
Table II. DAC Control Function
Input Register
Status
No Update
DAC Register
(Sleep/Wake)
No Change
Power-Down Status
Comments
No operation; power-down status unchanged
(part stays in Wake or Sleep Mode).
No Update
No Change
No Update
No Change
Not Used
Not Used
Not Used
Not Used
Not Used
Update Outputs
Wake
Update Outputs Wake
Update Outputs Wake
Load input Register A with data. DAC outputs
unchanged. Power-down status unchanged.
Load input Register B with data. DAC outputs
unchanged. Power-down status unchanged.
Load both DAC registers with existing contents
of input registers. Update DAC outputs. Part
wakes up.
Load input Register A. Load DAC registers with
new contents of input register A and existing
contents of Register B. Update DAC outputs.
Part wakes up.
Load input Register B. Load DAC registers with
new contents of input Register B and existing
contents of Register A. Update DAC outputs.
Part wakes up.
Not Used
Not Used
No Update
No Update
Update
Outputs
Wake
Sleep
Wake
Part wakes up. Input and DAC registers
unchanged. DAC outputs reflect existing
contents of DAC registers.
Power down the IC, put in into Sleep Mode.
Load both input registers. Load both DAC
registers with new contents of input registers.
Update DAC outputs. Part wakes up.
Modes of Operation
The ADD8502 has various modes of operation, such as updating
both DACs simultaneously or changing the power-down status
(Sleep/Wake). These are selected by writing the appropriate
4-bit control code (C0–C3). The details for each mode are
summarized in Table II.
Low Power Serial Interface
To reduce the power consumption of the device ever further, the
interface only powers up fully when the device is being written
to. As soon as the 16-bit control word has been written to the
part, the SCK and DIN input buffers are powered down. They
only power up again following a falling edge of CS-LD.
Double-Buffered Interface
The ADD8502 has double-buffered interfaces consisting of two
banks of registers: input and DAC. The input register is con-
nected directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC register contains the digital
code used by the resistor string.
Access to the DAC register is controlled by the control codes,
C0 to C3. The user can update both DACs simultaneously as
well as individually. It depends on the selected control codes to
update individual output or both outputs simultaneously.
Initial Power-Up Condition
The ADD8502 has preset DAC conditions when its initially
powered on. The DACs are loaded with 1110 1011 11 for the
upper DAC and 0000 1010 00 for the lower DAC. The part is
powered up in a normal operation mode (Wake Status).
Power-Down Modes
The ADD8502 has two shutdown modes. One mode is to fully
shut down the device using PSK or the digital serial control code,
and the other mode is to shut down V1 to V3 buffers using GS1
and GS2. See Table III for the priority of the shutdown control
functions.
–12–
REV. 0

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