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EP1S40 Schematic ( PDF Datasheet ) - Altera

Teilenummer EP1S40
Beschreibung (EP1S10 - EP1S80) Stratix Device
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EP1S40 Datasheet, Funktion
Section I. Stratix Device
Family Data Sheet
This section provides designers with the data sheet specifications for
Stratix devices. They contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
Chapter 1. Introduction
Chapter 2. Stratix Architecture
Chapter 3. Configuration & Testing
Chapter 4. DC & Switching Characteristics
Chapter 5. Reference & Ordering Information
Revision History The table below shows the revision history for Chapter 1 through
Chapter 5.
Chapter
Date/Version
Changes Made
1 September 2004, v3.1 Updated Table 1–6 on page 1–5.
April 2004, v3.0 Main section page numbers changed on first page.
Changed PCI-X to PCI-X 1.0 in “Features” on page 1–2.
Global change from SignalTap to SignalTap II.
mJanuary 2004, v2.2
.coOctober 2003, v2.1
uJuly 2003, v2.0
The DSP blocks in “Features” on page 1–2 provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”
Updated -5 speed grade device information in Table 1-6.
Add -8 speed grade device information.
Format changes throughout chapter.
www.datasheet4Altera Corporation
Section I–1
Preliminary






EP1S40 Datasheet, Funktion
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
4
5
Date/Version
Changes Made
October 2003, v2.1
Added -8 speed grade information.
Updated performance information in Table 4–36.
Updated timing information in Tables 4–55 through 4–96.
Updated delay information in Tables 4–103 through 4–108.
Updated programmable delay information in Tables 4–100 and
4–103.
July 2003, v2.0
Updated clock rates in Tables 4–114 through 4–123.
Updated speed grade information in the introduction on page 4-1.
Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD
are specified.
Added note 6 to Table 4-32.
Updated Stratix Performance Table 4-35.
Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to
4-93. The Stratix timing models are final for all devices.
Updated Stratix IOE programmable delay chains in Tables 4-100 to
4-101.
Added single-ended I/O standard output pin delay adders for loading
in Table 4-102.
Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107.
Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-
115.
Updated EPLL specification and fast PLL specification in Tables 4-
116 to 4-120.
September 2004, v2.1 Updated reference to device pin-outs on page 5–1 to indicate that
device pin-outs are no longer included in this manual and are now
available on the Altera web site.
April 2003, v1.0 No new changes in Stratix Device Handbook v2.0.
1–6
Preliminary
Altera Corporation

6 Page









EP1S40 pdf, datenblatt
Features
1–6 Core Version a.b.c variable
Stratix Device Handbook, Volume 1
Altera Corporation
September 2004

12 Page





SeitenGesamt 30 Seiten
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