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PDF DS1644P Data sheet ( Hoja de datos )
| Número de pieza | DS1644P | |
| Descripción | Nonvolatile Timekeeping RAM | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS1644/DS1644P
Nonvolatile Timekeeping RAM
www.maxim-ic.com
FEATURES
§ Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
§ Clock Registers are Accessed Identically to
the Static RAM. These Registers are
Resident in the Eight Top RAM Locations.
§ Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
§ BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100
§ Power-Fail Write Protection Allows for
±10% VCC Power Supply Tolerance
§ DS1644 Only (DIP Module)
Upward Compatible with the DS1643
Timekeeping RAM to Achieve Higher
RAM Density
Standard JEDEC Bytewide 32k x 8 Static
RAM Pinout
§ DS1644P Only (PowerCap® Module Board)
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and crystal
Replaceable Battery (PowerCap)
Power-Fail Output
Pin-for-Pin Compatible with Other Densities
of DS164XP Timekeeping RAM
Underwriters Laboratory (UL) Recognized
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
28-Pin Encapsulated Package
(720-mil Extended)
NC
NC
NC
PVFCOC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X1
17
GND VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap is a registered trademark of Dallas Semiconductor.
ORDERING INFORMATION
PART
VOLTAGE
RANGE (V)
TEMP RANGE PIN-PACKAGE
DS16440120+
5.0
0°C to +70°C 32 EDIP (0.740a)
DS16440-120
5.0
0°C to +70°C 32 EDIP (0.740a)
DS1644P120+
5.0
0°C to +70°C 34 PowerCap*
DS1644P-120
5.0
0°C to +70°C 34 PowerCap*
TOP MARK
DS1644+120
DS1644-120
DS1644P+120
DS1644P-120
*DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately).
A “+" indicates a lead-free product. The top mark will include a “+" symbol on lead-free devices.
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DS1644/DS1644P
DS1644 REGISTER MAP—BANK1 Table 2
ADDRESS B7
B6
B5
DATA
B4 B3
B2
B1
B0
7FFF
— ———————
FUNCTION
Year
00-99
7FFE
X X X — — — — — Month 01-12
7FFD
X X - — — — — — Date 01-31
7FFC
X FT X X X — — — Day 01-07
7FFB
X X — — — — — — Hour 00-23
7FFA
X — — — — — — — Minutes 00-59
7FF9
OSC — — — — — — — Seconds 00-59
7FF8
W R X X X X X X Control
A
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
Note: All indicated “X” bits are unused but must be set to “0” during write cycles to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE or CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
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DS1644/DS1644P
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is calculated from the date code on the device package. The date
code XXYY is the year followed by the week of the year in which the device was manufactured. For
example, 9225 would mean the 25th week of 1992.
5. tAH1, tDH1 are measured from WE going high.
6. tAH2, tDH2 are measured from CE going high.
7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live - bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet DS1644P.PDF ] | |
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