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PDF ADP3188 Data sheet ( Hoja de datos )
| Número de pieza | ADP3188 | |
| Descripción | Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3188 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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6-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
ADP3188
FEATURES
Selectable 2-, 3- or 4-phase operation at up to
1 MHz per phase
±9.5 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external
high power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next-generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3188 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. The part uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage between
0.8375 V and 1.6 V. It uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency.
The phase relationship of the output signals can be pro-
grammed to provide 2-, 3-, or 4-phase operation, allowing
the construction of up to four complementary buck
switching stages.
The ADP3188 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of
the load current, so it is always optimally positioned for a system
transient. The ADP3188 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The ADP3188 is specified over the commercial tempera-
ture range of 0°C to 85°C and is available in 28-lead, TSSOP
and QSOP packages.
EN 11
GND 19
FUNCTIONAL BLOCK DIAGRAM
VCC
28
UVLO
SHUTDOWN
AND BIAS
RAMPADJ RT
14 13
ADP3188
OSCILLATOR
SET EN
CMP RESET
27 PWM1
DAC+150mV
CSREF
DAC-250mV
PWRGD 10
DELAY
CURRENT
BALANCING
CIRCUIT
CMP
CMP
RESET
2-/3-/4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
CMP RESET
CROWBAR
24 PWM4
CURRENT
LIMIT
ILIMIT 15
EN
DELAY 12
SOFT
START
CURRENT
LIMIT
CIRCUIT
23 SW1
22 SW2
21 SW3
20 SW4
17 CSSUM
16 CSREF
18 CSCOMP
COMP 9
8 FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
1 23456
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
TEST CIRCUITS
ADP3188
1 VID4
VCC 28
2 VID3
PWM1 27
+1µF
6-BIT CODE
3 VID2
4 VID1
PWM2 26
PWM3 25
5 VID0
PWM4 24
6 VID5
SW1 23
7 FBRTN
SW2 22
8 FB
SW3 21
9 COMP
1k Ω
10 PWRGD
SW4 20
GND 19
1.25V
12nF 250kΩ
11 EN
12 DELAY
13 RT
CSCOMP 18
20kΩ
CSSUM 17
CSREF 16
14 RAMPADJ
ILIMIT 15
250kΩ
12V
100n F
100nF
Figure 2. Closed-Loop Output Voltage Accuracy
ADP3188
12V
39kΩ
1kΩ
1.0V
ADP3188
VCC
28
CSCOMP
18
100nF
CSSUM
17
CSREF
16
GND
19
VOS =
CSCOMP – 1V
40
Figure 3. Current-Sense Amplifier VOS
12V
10kΩ
200kΩ
200kΩ 100nF
∆V
1.0V
ADP3188
VCC
28
FB
8
COMP
9
CSCOMP
18
CSSUM
17
CSREF
16
GND
19
∆VFB = FB∆V = 80mV – FB∆V = 0mV
Figure 4. Positioning Voltage
Rev. A | Page 5 of 28
5 Page 
ADP3188
Figure 8. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3188 compares a programmable current-limit setpoint
to the voltage from the output of the current-sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current-limit threshold of 10.4 mV/µA. If the
difference in voltage between CSREF and CSCOMP rises above
the current-limit threshold, the internal current-limit ampli-
fier controls the internal COMP voltage to maintain the average
output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current-limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V.
The Application Information section discusses the selection of
CDLY and RDLY.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD thresh-
old, a soft-start cycle is initiated.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3188, or by pulling the EN pin
low for a short time. To disable the short-circuit latch-off
function, the external resistor to ground should be left open,
and a high value (>1 MΩ) resistor should be connected from
DELAY to VCC. This prevents the DELAY capacitor from
discharging, so the 1.8 V threshold is never reached. The resistor
has an impact on the soft-start time because the current through
it adds to the internal 20 µA current source.
During start-up when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit controls the internal COMP
voltage to the PWM comparators to 2 V. This limits the
voltage drop across the low-side MOSFETs through the
current balance circuitry.
An inherent per phase current limit protects individual phases,
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
Figure 9. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3188 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID on-
the-fly (OTF). A VID OTF can occur under either light or
heavy load conditions. The processor signals the controller by
changing the VID inputs in multiple steps from the start code
to the finish code. This change can be positive or negative.
When a VID input changes state, the ADP3188 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and crowbar blanking functions for a
minimum of 100 µs to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.
Rev. A | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADP3188.PDF ] | |
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