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PDF ADP3181 Data sheet ( Hoja de datos )
| Número de pieza | ADP3181 | |
| Descripción | Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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5-Bit or 6-Bit Programmable 2-,3-,4-Phase
Synchronous Buck Controller
ADP3181
FEATURES
Selectable 2-, 3- or 4-phase operation at up to 1 MHz per
phase
±14.5 mV worst-case mV differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable output can be switched between
VRM 9 (5-bit) and VRD 10 (6-bit) VID codes
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for:
Next-generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3181 is a highly efficient multiphase synchronous
buck-switching regulator controller optimized for converting
a 12 V main supply into the core supply voltage required by
high performance Intel processors. It uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage. The
CPUID input selects whether the DAC codes match the
VRM 9 or VRD 10 specifications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can
be programmed to provide 2-, 3-, or 4-phase operation,
allowing for the construction of up to four complementary
buck-switching stages.
The ADP3181 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3181 provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The device is specified over the commercial temperature range
of 0°C to +85°C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
28
EN 11
UVLO
SHUTDOWN
AND BIAS
GND 19
DAC + 300mV
CSREF
DAC – 250mV
PWRGD 10
DELAY
RAMPADJ RT
14 13
OSCILLATOR
CMP
ADP3181
SET EN
RESET
27 PWM1
CURRENT-
BALANCING
CIRCUIT
CMP
CMP
RESET
2-/3-/4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
CMP RESET
24 PWM4
CROWBAR
CURRENT
LIMIT
ILIMIT 15
EN
DELAY 12
COMP 9
SOFT
START
CURRENT-
LIMITING
CIRCUIT
23 SW1
22 SW2
21 SW3
20 SW4
17 CSSUM
16 CSREF
18 CSCOMP
8 FB
http://www.DataSheet4U.net/
PRECISION
REFERENCE
VID
DAC
76
FBRTN CPUID
1 2 34 5
VID4 VID3 VID2 VID1 VID0
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
datasheet pdf - http://www.DataSheet4U.net/
1 page  
TEST CIRCUITS
ADP3181
1 VID4
VCC 28
2 VID3
PWM1 27
+ 1µF
5-BIT CODE
3 VID2
4 VID1
PWM2 26
PWM3 25
5 VID0
PWM4 24
6 CPUID
SW1 23
7 FBRTN
SW2 22
8 FB
SW3 21
9 COMP
1kΩ
10 PWRGD
SW4 20
GND 19
1.25V
11 EN
12 DELAY
CSCOMP 18
20kΩ
CSSUM 17
12nF
250kΩ 13 RT
CSREF 16
14 RAMPADJ ILIMIT 15
250kΩ
12V
100nF
100nF
Figure 2. Closed-Loop Output Voltage Accuracy
12V
39kΩ
1kΩ
1.0V
ADP3181
VCC
28
CSCOMP
18
100nF
CSSUM
17
CSREF
16
GND
19
VOS
=
CSCOMP–1V
40
Figure 3. Current Sense Amplifier VOS
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ADP3181
ADP3181
VCC
12V 28
10kΩ
FB
8
COMP
9
200kΩ
∆V
1.0V
200kΩ
100nF
CSCOMP
18
CSSUM
17
CSREF
16
GND
19
∆VFB = FB∆V = 80mV – FB∆V = 0mV
Figure 4. Positioning Voltage
Rev. 0 | Page 5 of 24
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
ADP3181
OUTPUT CURRENT SENSING
The ADP3181 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:
• Output inductor ESR sensing without a thermistor for
lowest cost.
• Output inductor ESR sensing with a thermistor for
improved accuracy with tracking of inductor temperature.
• Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor. The
current information is then given as the difference of CSREF –
CSCOMP. This difference signal is used internally to offset the
VID DAC for voltage positioning and as a differential input for
the current limit comparator.
To provide the best accuracy for the sensing of current, the CSA
has been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to equal the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the
system. The droop voltage is subtracted from the DAC reference
input voltage directly to tell the error amplifier where the output
voltage should be. This differs from previous implementations
and allows enhanced feed-forward response.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3181 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the positioning
described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It is also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.
If desired, external resistors can be placed in series with
individual phases to create an intentional current imbalance if
desired, such as when one phase may have better cooling and
can support higher currents. Resistors RSW1 through RSW4
(see the typical application circuit in Figure 10) can be used for
adjusting thermal balance. It is best to have the ability to add
these resistors during the initial design, so make sure
placeholders are provided in the layout.
http://www.DataSheet4U.net/
To increase the current in any phase, make RSW for that phase
larger (make RSW = 0 for the hottest phase; do not change during
balancing). Increasing RSW to only 500 Ω makes a substantial
increase in phase current. Increase each RSW value by small
amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic. This voltage is also offset
by the droop voltage for active positioning of the output voltage
as a function of current, commonly known as active voltage
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor, RB, and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated in
the feedback network between FB and COMP.
Rev. 0 | Page 11 of 24
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADP3181.PDF ] | |
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