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Teilenummer | EPM1270 |
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Beschreibung | (EPMxxxx) JTAG & In-System Programmability | |
Hersteller | Altera Corporation | |
Logo | ||
Gesamt 30 Seiten Section I. MAX II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
MAX® II devices. The chapters contain feature definitions of the internal
architecture, Joint Test Action Group (JTAG) and in-system
programmability (ISP) information, DC operating conditions, AC timing
parameters, and ordering information for MAX II devices.
This section includes the following chapters:
■ Chapter 1. Introduction
■ Chapter 2. MAX II Architecture
■ Chapter 3. JTAG & In-System Programmability
■ Chapter 4. Hot Socketing & Power-On Reset in MAX II Devices
■ Chapter 5. DC & Switching Characteristics
■ Chapter 6. Reference & Ordering Information
Altera Corporation
Section I–1
Preliminary
Features
Table 1–4. MAX II TQPF & FineLine BGA Package Sizes
Package
Pitch (mm)
Area (mm2)
Length x width
(mm x mm)
100-Pin TQFP
0.5
256
16 × 16
144-Pin TQFP
0.5
484
22 × 22
256-Pin FineLine BGA 324-Pin FineLine BGA
11
289 361
17 × 17
19 × 19
MAX II devices have an internal linear voltage regulator which supports
external supply voltages of 3.3 V or 2.5 V, regulating the supply down to
the internal operating voltage of 1.8 V. MAX IIG devices only accept 1.8 V
as an external supply voltage. Table 1–5 shows the external supply
voltages supported by the MAX II family.
Table 1–5. MAX II External Supply Voltages
Devices
EPM240
EPM570
EPM1270
EPM2210
EPM240G
EPM570G
EPM1270G
EPM2210G
(1)
MultiVolt core external
supply voltage (VCCINT)
(2)
MultiVolt I/O interface
voltage levels (VCCIO)
3.3 V, 2.5 V
1.8 V
1.5 V, 1.8 V, 2.5 V, 3.3 V 1.5 V, 1.8 V, 2.5 V, 3.3 V
Notes to Table 1–5:
(1) MAX IIG devices do not have an internal voltage regulator and only accept 1.8 V
on their VCCINT pins. Contact Altera for availability on these devices.
(2) MAX II devices operate internally at 1.8 V.
1–4 Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
December 2004
6 Page Logic Array Blocks
Figure 2–4. DirectLink Connection
DirectLink interconnect from
left LAB or IOE output
DirectLink
interconnect
to left
Local
Interconnect
Logic Element
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LAB
DirectLink interconnect from
right LAB or IOE output
DirectLink
interconnect
to right
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, a synchronous clear, an asynchronous preset/load,
a synchronous load, and add/subtract control signals, providing a
maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal also uses labclkena1. If the
LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal turns off the
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
2–6 Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
December 2004
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EPM1270 Schematic.PDF ] |
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