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PDF DM9602 Data sheet ( Hoja de datos )
| Número de pieza | DM9602 | |
| Descripción | Dual Retriggerable Resettable One Shots | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1986
Revised February 2000
DM9602
Dual Retriggerable, Resettable One Shots
General Description
These dual resettable, retriggerable one shots have two
inputs per function; one which is active HIGH, and one
which is active LOW. This allows the designer to employ
either leading-edge or trailing-edge triggering, which is
independent of input transition times. When input condi-
tions for triggering are met, a new cycle starts and the
external capacitor is allowed to rapidly discharge and then
charge again. The retriggerable feature permits output
pulse widths to be extended. In fact a continuous true out-
put can be maintained by having an input cycle time which
is shorter than the output cycle time. The output pulse may
then be terminated at any time by applying a LOW logic
level to the RESET pin. Retriggering may be inhibited by
either connecting the Q output to an active HIGH input, or
the Q output to an active LOW input.
Features
s 70 ns to ∞ output width range
s Resettable and retriggerable—0% to 100% duty cycle
s TTL input gating—leading or trailing edge triggering
s Complementary TTL outputs
s Optional retrigger lock-out capability
s Pulse width compensated for VCC and temperature vari-
ations
Ordering Code:
Order Number Package Number
Package Description
DM9602N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Logic Diagrams
Function Table
Pin Numbers
AB
H→L
L
H L→H
XX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
CLR
H
H
L
Operation
Trigger
Trigger
Reset
© 2000 Fairchild Semiconductor Corporation DS006611
www.fairchildsemi.com
1 page  
Switching Characteristics
VCC = 5V, TA = 25°C
Symbol
Parameter
tPLH
tPHL
tPW(MIN)
tPW
Propagation Delay Time,
LOW-to-HIGH Level Output
Propagation Delay Time,
HIGH-to-LOW Level Output
Minimum True Output
Pulse Width
Minimum Complement
Pulse Width
Pulse Width
Negative Trigger Input
to True Output
Negative Trigger Input
To Complement Output
CSTRAY
RX
Maximum Allowable Wiring
Capacitance
External Timing Resistor
Conditions
CL = 15 pF
CX = 0
RX = 5 kΩ
RX = 10 kΩ
CX = 1000 pF
Pins 2, 14 to GND
Min
3.08
5
Max
40
Units
ns
48 ns
100
ns
110
3.76
µs
50 pF
50 kΩ
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DM9602.PDF ] | |
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