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DS3252 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS3252
Beschreibung (DS3251 - DS3254) Single / Dual / Triple / Quad DS3/E3/STS-1 LIUs
Hersteller Maxim Integrated Products
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Gesamt 30 Seiten
DS3252 Datasheet, Funktion
DS3251/DS3252/DS3253/DS3254
Single/Dual/Triple/Quad
DS3/E3/STS-1 LIUs
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3251 (single), DS3252 (dual), DS3253
(triple), and DS3254 (quad) line interface units (LIUs)
perform the functions necessary for interfacing at the
physical layer to DS3, E3, or STS-1 lines. Each LIU
has independent receive and transmit paths and a
built-in jitter attenuator. An on-chip clock adapter
generates all line-rate clocks from a single input
clock. Control interface options include 8-bit parallel,
SPI, and hardware mode.
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSU/DSUs
FUNCTIONAL DIAGRAM
LINE IN
DS3, E3,
OR STS-1
LINE OUT
DS3, E3,
OR STS-1
EACH LIU
RXP
RXN
CLK
DATA
Dallas
Semiconductor
DS325x
TXP
TXN
CLK
DATA
RECEIVE
CLOCK
AND DATA
CONTROL
STATUS
TRANSMIT
CLOCK
AND DATA
FEATURES
§ Pin-Compatible Family of Products
§ Each Port Independently Configurable
§ Receive Clock and Data Recovery for Up to 380
meters (DS3), 440 meters (E3), or 360 meters
(STS-1) of 75W Coaxial Cable
§ Standards-Compliant Transmit Waveshaping
§ Three Control Interface Options: 8-Bit Parallel,
SPI, and Hardware Mode
§ Built-In Jitter Attenuators can be Placed in Either
the Receive or Transmit Paths
§ Jitter Attenuators Have Provisionable Buffer
Depth: 16, 32, 64, or 128 Bits
§ Built-In Clock Adapter Generates All Line-Rate
Clocks from a Single Input Clock (DS3, E3,
STS-1, OC-3, 19.44MHz, 38.88MHz,
77.76MHz)
§ B3ZS/HDB3 Encoding and Decoding
§ Minimal External Components Required
§ Local and Remote Loopbacks
§ Low-Power 3.3V Operation (5V Tolerant I/O)
§ Industrial Temperature Range: -40°C to +85°C
§ Small Package: 144-Pin, 13mm x 13mm
Thermally Enhanced CSBGA
§ Drop-In Replacement for DS3151/52/53/54 LIUs
§ IEEE 1149.1 JTAG Support
Features continued on page 5.
ORDERING INFORMATION
PART
LIU TEMP RANGE PIN-PACKAGE
DS3251
DS3251N
DS3252
DS3252N
DS3253
DS3253N
DS3254
DS3254N
1 0°C to +70°C 144 TE-CSBGA
1 -40°C to +85°C 144 TE-CSBGA
2 0°C to +70°C 144 TE-CSBGA
2 -40°C to +85°C 144 TE-CSBGA
3 0°C to +70°C 144 TE-CSBGA
3 -40°C to +85°C 144 TE-CSBGA
4 0°C to +70°C 144 TE-CSBGA
4 -40°C to +85°C 144 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS3252 Datasheet, Funktion
1. STANDARDS COMPLIANCE
DS3251/DS3252/DS3253/DS3254
Table 1-A. Applicable Telecommunications Standards
SPECIFICATION
SPECIFICATION TITLE
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
G.703
G.751
G.775
G.823
G.824
O.151
ETS 300 686
ETS 300 687
ETS EN 300 689
TBR 24
GR-253-CORE
GR-499-CORE
ANSI
Digital Hierarchy—Electrical Interfaces
Digital Hierarchy—Formats Specification
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation—DS3 Metallic Interface Specification
ITU-T
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the
Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993
Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November 1994
The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps
Hierarchy, 1993
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October 1992
ETSI
Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U,
D34S, D140U, and D140S); Network Interface Presentation, 1996
Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S);
Connection Characteristics, 1996
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines;
Attachment Requirements for Terminal Equipment Interface, 1997
TELCORDIA
SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1,
December 1998
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DS3252 pdf, datenblatt
DS3251/DS3252/DS3253/DS3254
Table 6-D. Hardware Mode Pin Descriptions
Note: These pins are active in hardware mode.
NAME
E3Mn
STSn
LLBn,
RLBn
RBIN
RCINV
RJAn
RMONn
TBIN
TCINV
TDSAn,
TDSBn
TJAn
TLBOn
TYPE
I
I
I
I
I
I
I
I
I
I
I
I
FUNCTION
E3 Mode Enable
0 = DS3 operation
1 = E3 or STS-1 operation
STS-1 Mode Enable
When E3M = 1,
0 = E3 operation
1 = STS-1 operation
When E3M = 0, STS selects the DS3 AIS pattern. See Table 6-G.
Local Loopback Select, Remote Loopback Select
{LLB, RLB} = 00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
Receiver Binary Framer-Interface Enable
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code
violations. The B3ZS/HDB3 encoder is enabled.
Receiver Clock Invert
0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.
Receiver Jitter Attenuator Enable
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
See Table 6-I for more information.
Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is enabled
to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This feature
should be enabled when the device is being used to monitor signals that have been resistively
attenuated by a monitor jack. See Section 8.2 for more information.
0 = disable the monitor preamp
1 = enable the monitor preamp
Transmitter Binary Framer-Interface Enable
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is
disabled.
1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired low.)
The B3ZS/HDB3 encoder is enabled.
Transmitter Clock Invert
0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
Transmitter Data Select. These inputs select the source of the transmit data. See Table 6-G for
details.
Transmitter Jitter Attenuator Enable
0 = remove jitter attenuator from the transmitter path
1 = insert jitter attenuator into the transmitter path
See Table 6-I for more information.
Transmitter Line Build-Out Enable. TLBO indicates cable length for waveform shaping in DS3 and
STS-1 modes. TLBO is ignored for E3 mode and should be wired high or low.
0 = cable length ³ 225ft
1 = cable length < 225ft
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