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DPA423 Schematic ( PDF Datasheet ) - Power Integrations

Teilenummer DPA423
Beschreibung (DPA423 - DPA426) Highly Integrated DC-DC Converter ICs for Distributed Power Architectures
Hersteller Power Integrations
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Gesamt 36 Seiten
DPA423 Datasheet, Funktion
DPA423-426
DPA-SwitchFamily
Highly Integrated DC-DC Converter ICs
for Distributed Power Architectures
Product Highlights
Highly Integrated Solution
• Eliminates 20-50 external components–saves space, cost
• Integrates 220 V high frequency MOSFET, PWM control
• Lower cost plastic DIP surface mount (G package) and
through-hole (P package) options for designs 35 W
Superior Performance and Flexibility
• Eliminates all external current sensing circuitry
• Built-in auto-restart for output overload/open loop protection
• Pin selectable 300/400 kHz fixed frequency
• Wide input (line) voltage range: 16-75 VDC
• Source connected tab reduces EMI
• Line under-voltage (UV) detection: meets ETSI standards
• Line overvoltage (OV) shutdown protection
• Low cost synchronous rectification: line UV/OV shut down
limits gate drive voltage range from transformer winding
• Fully integrated soft-start for minimum stress/overshoot
• Externally programmable current limit
• Supports forward or flyback topology
• Cycle skipping: regulation to zero load without pre-load
• Hysteretic thermal shutdown for automatic fault recovery
EcoSmart ®- Energy Efficient
• Extremely low consumption at no load
• Cycle skipping at light load for high standby efficiency
Applications
• Telco central office equipment: xDSL, ISDN, PABX, etc.
• Distributed power architectures (24 V/48 V bus, etc.)
• Digital feature phones, VoIP phones, PoE
• Industrial controls (24 V/48 V)
Description
The DPA-Switch IC family introduces a highly integrated
solution for DC-DC conversion applications in the 16-75 VDC
input range.
DPA-Switch uses the same proven topology as TOPSwitch, cost
effectively integrating the high voltage power MOSFET, PWM
control, fault protection and other control circuitry onto a single
CMOS chip. High performance features are enabled with three
user configurable pins.
DPA-Switch
VIN D
RESET/
CLAMP
CIRCUIT
S
L
CONTROL
C
XF
VO
SENSE
CIRCUIT
Figure 1. Typical Forward Converter Application.
PI-2770-032002
OUTPUT POWER TABLE
36-75 VDC INPUT RANGE (FORWARD)2,4
Total Device
Dissipation3 0.5 W 1 W 2.5 W 4 W
PRODUCT4
Max
6 W Power
Output1
DPA423 12 W 16 W - - - 18 W
DPA424 16 W 23 W 35 W - - 35 W
DPA425 23 W 32 W 50 W 62 W - 70 W
DPA426 25 W 35 W 55 W 70 W 83 W 100 W
36-75 VDC INPUT RANGE (FLYBACK)2
Total Device3
Dissipation 0.5 W
PRODUCT4
0.75 W
1W
Max
1.5 W Power
Output1
DPA423 9 W 13 W -
- 13 W
DPA424 10 W 14.5 W 18 W 24 W 26 W
DPA425
-5
-5
-5 25.5 W 52 W
Table 1. Notes: 1. Maximum output power is limited by device internal
current limit. 2. See Applications Considerations section for complete
description of assumptions and for output powers with other input voltage
ranges. 3. For device dissipation of 1.5 W or below, use P or G packages.
Device dissipation above 1.5 W is possible only with R package. 4. See
Part Ordering Information. 5. Due to higher switching losses, the DPA425
may not deliver additional power compared to a smaller device.
The following transparent or built-in features are also provided:
soft-start, cycle skipping down to zero load and hysteretic
thermal shutdown. In addition, all critical parameters (i.e.
current limit, frequency, PWM gain) have tight temperature
and absolute tolerance, to simplify design and optimize system
cost.
January 2004






DPA423 Datasheet, Funktion
DPA423-426
Pulse Width Modulator and Maximum Duty Cycle
The pulse width modulator implements voltage mode control
by driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that is in
excess of the internal supply current of the chip (see Figure 4).
The excess current is the feedback error signal that appears
across RE (see Figure 2). This signal is filtered by an RC network
with a typical corner frequency of 30 kHz to reduce the effect
of switching noise in the chip supply current generated by the
MOSFET gate driver. The filtered error signal is compared with
the internal oscillator sawtooth waveform to generate the duty
cycle waveform. As the control current increases, the duty cycle
decreases. A clock signal from the oscillator sets a latch that
turns on the output MOSFET. The pulse width modulator resets
the latch, turning off the output MOSFET. Note that a minimum
current must be driven into the CONTROL pin before the duty
cycle begins to change.
The maximum duty cycle, DCMAX is set at a default maximum
value of 75% (typical). However, by connecting the
LINE-SENSE to the DC input bus through a resistor with
appropriate value, the maximum duty cycle can be made to
decrease from 75% to 33% (typical) as shown in
Figure 7 when input line voltage increases (see line feed
forward with DC reduction).
MAX
Minimum Duty Cycle and Cycle Skipping
To maintain power supply output regulation, the pulse width
modulator reduces duty cycle as the load at the power supply
output decreases. This reduction in duty cycle is proportional to
the current flowing into the CONTROL pin. As the CONTROL
pin current increases, the duty cycle reduces linearly towards a
minimum value specified as minimum duty cycle, DC . After
MIN
reaching DCMIN, if CONTROL pin current is increased further
by approximately 2 mA, the pulse width modulator will force
the duty cycle from DCMIN to zero in a discrete step (refer to
Figure 4). This feature allows a power supply to operate in a
cycle skipping mode when the load consumes less power than
the DPA-Switch delivers at minimum duty cycle, DCMIN. No
additional control is needed for the transition between normal
operation and cycle skipping. As the load increases or decreases,
the power supply automatically switches between normal and
cycle skipping mode as necessary.
Cycle skipping may be avoided, if so desired, by connecting a
minimum load at the power supply output such that the duty
cycle remains at a level higher than DCMIN at all times.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifier in primary side feedback applications. The shunt
regulator voltage is accurately derived from a temperature-
compensated bandgap reference. The gain of the error amplifier
is set by the CONTROL pin dynamic impedance. The
CONTROL pin clamps external circuit signals to the VC voltage
6K
1/04
level. The CONTROL pin current in excess of the supply
current is separated by the shunt regulator and flows through RE
as a voltage error signal.
On-chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage, V with a threshold voltage. At the
DS(ON)
current limit, VDS(ON) exceeds the threshold voltage and the
MOSFET is turned off until the start of the next clock cycle. The
current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
to temperature related changes in RDS(ON) of the output MOSFET.
The default current limit of DPA-Switch is preset internally.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT pin and SOURCE pin, the current limit can
be programmed externally to a lower level between 25% and
100% of the default current limit. Please refer to the graphs in
the Typical Performance Characteristics section for the
selection of the resistor value. By setting current limit low, a
larger DPA-Switch than necessary for the power required can be
used to take advantage of the lower RDS(ON)for higher efficiency/
smaller heat sinking requirements. With a second resistor
connected between the EXTERNAL CURRENT LIMIT pin
and the DC input bus, the current limit is reduced with increasing
line voltage, allowing a true power limiting operation against
line variation to be implemented in a flyback configuration.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitance and secondary-side rectifier reverse
recovery time should not cause premature termination of the
switching pulse.
The current limit after the leading edge blanking time is as
shown in Figure 31. To avoid triggering the current limit in
normal operation, the drain current waveform should stay
within the envelope shown.
Line Under-Voltage Detection (UV)
At power up, UV keeps DPA-Switch off until the input line
voltage reaches the under voltage upper threshold. At power
down, UV holds DPA-Switch on until the input voltage falls
below the under voltage lower threshold. A single resistor
connected from the LINE-SENSE pin to the DC input bus sets
UV upper and lower thresholds. To avoid false triggering by
noise, a hysteresis is implemented which sets the UV lower
threshold typically at 94% of the UV upper threshold. If the UV
lower threshold is reached during operation without the power
supply losing regulation and the condition stays longer than
10 µs (typical), the device will turn off and stay off until the UV
upper threshold has been reached again. Then, a soft-start

6 Page









DPA423 pdf, datenblatt
DPA423-426
Typical Uses of FREQUENCY (F) Pin
+
+
DC
Input
Voltage
D
CONTROL
C
SF
DC
Input
Voltage
D
CONTROL
C
SF
--
PI-2654-071700
PI-2655-071700
Figure 9. 400 kHz Frequency Operation.
Figure 10. 300 kHz Frequency Operation.
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins
+
DC
Input
Voltage
CL X S F D
DL
CONTROL
C
CS D
- S XF
PI-2766-070901
Figure 11. Three Terminal Operation (LINE-SENSE and
EXTERNAL CURRENT LIMIT Features Disabled.
FREQUENCY Pin can be tied to SOURCE or
CONTROL Pin).
+
DC
Input
Voltage
6.2 V
576 k
1%
VUV = RLS x IUV +
VL (IL = IUV)
RLS
For Values Shown
VUV = 33.3 V
42.2 k
1%
DL
CONTROL
C
-S
PI-2852-091302
Figure 13. Line-Sensing for Under-Voltage Only (Overvoltage
Disabled).
12 K
1/04
+
DC
Input
Voltage
VUV = IUV x RLS + VL (IL = IUV)
VOV = IOV x RLS + VL (IL = IOV)
RLS
619 k
1%
DL
CONTROL
C
For RLS = 619 k
VUV = 33.3 V
VOV = 86.0 V
-S
PI-2767-091302
Figure 12. Line-Sensing for Under-Voltage, Overvoltage and
Line Feed Forward.
+
DC
Input
Voltage
590 k
1%
RLS
30 k
1%
DL
CONTROL
C
VOV = IOV x RLS +
VL (IL = IOV)
For Values Shown
VOV = 86.2 V
1N4148
-S
PI-2853-091302
Figure 14. Line-Sensing for Overvoltage Only (Under-Voltage
Disabled). Maximum Duty Cycle will be reduced at
Low Line.

12 Page





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