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CAT24C02 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT24C02
Beschreibung (CAT24C01 - CAT24C16) Serial EPROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 17 Seiten
CAT24C02 Datasheet, Funktion
CAT24C01/02/04/08/16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
For Ordering Information details, see page 16.
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices support
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
MSOP (Z)
TDFN (VP2)
CAT24C16 / 08 / 04 / 02 / 01
NC / NC / NC / A0 / A0
NC / NC / A1 / A1 / A1
NC / A2 / A2 / A2 / A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
www.DataSheet4U.com
FUNCTIONAL SYMBOL
TSOT-23 (TD)
SCL 1
VSS 2
SDA 3
5 WP
4 VCC
SCL
A2, A1, A0
VCC
CAT24Cxx
SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2
SDA
SCL
WP
VCC
VSS
NC
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
WP
VSS
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1115, Rev. C






CAT24C02 Datasheet, Funktion
CAT24C01/02/04/08/16
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START condi-
tion and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge,
the Master sends the byte address that is to be written
into the address pointer of the CAT24Cxx. After receiv-
ing another acknowledge from the Slave, the Master
transmits the data byte to be written into the addressed
memory location. The CAT24Cxx device will acknowl-
edge the data byte and the Master generates the STOP
condition, at which time the device begins its internal
Write cycle to nonvolatile memory (Figure 5). While this
internal cycle is in progress (tWR), the SDA output will
be tri-stated and the CAT24Cxx will not respond to any
request from the Master device (Figure 6).
Page Write
The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 7).
The Page Write operation is initiated in the same manner
as the Byte Write operation, however instead of termi-
nating after the data byte is transmitted, the Master is
allowed to send up to fifteen additional bytes. After each
byte has been transmitted the CAT24Cxx will respond
with an acknowledge and internally increments the four
low order address bits. The high order bits that define
the page address remain unchanged. If the Master
transmits more than sixteen bytes prior to sending the
STOP condition, the address counter ‘wraps around’ to
the beginning of page and previously transmitted data
will be overwritten. Once all sixteen bytes are received
and the STOP condition has been sent by the Master,
the internal Write cycle begins. At this point all received
data is written to the CAT24Cxx in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the host’s
write operation, the CAT24Cxx initiates the internal write
cycle. TheACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still
busy with the write operation, NoACK will be returned. If
the CAT24Cxx has completed the internal write operation,
an ACK will be returned and the host can then proceed
with the next read or write operation.
Hardware Write Protection
With the WPpin held HIGH, the entire memory is protected
against Write operations. If the WP pin is left floating or
is grounded, it has no impact on the operation of the
CAT24Cxx. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first
data byte (Figure 8). If the WP pin is HIGH during the
strobe interval, the CAT24Cxx will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24Cxx is shipped erased, i.e., all bytes are
FFh.
Doc. No. 1115, Rev. C
6
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

6 Page









CAT24C02 pdf, datenblatt
CAT24C01/02/04/08/16
8-Lead TSSOP (Y)
D
85
E
E/2
E1
PIN #1 IDENT.
1
A
e
4
A2
A1
b
θ1
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
θ1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.50
0.00
NOM
0.90
3.00
6.4
4.40
0.65 BSC
0.60
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.75
8.00
SEE DETAIL A
c
GAGE PLANE
0.25
L SEATING PLANE
SEE DETAIL A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-153.
Doc. No. 1115, Rev. C
12
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

12 Page





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