Datenblatt-pdf.com


ADCMP564 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADCMP564
Beschreibung (ADCMP563 / ADCMP564) Dual High Speed ECL Comparators
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADCMP564 Datasheet, Funktion
Dual High Speed ECL Comparators
ADCMP563/ADCMP564
FEATURES
Differential ECL compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
FUNCTIONAL BLOCK DIAGRAM
HYS*
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP563/
ADCMP564
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
*ADCMP564 ONLY
Figure 1.
QA 1
16 QB
QA 2
15 QB
GND 3
LEA 4
LEA 5
ADCMP563
TOP VIEW
(Not to Scale)
14 GND
13 LEB
12 LEB
VEE 6
–INA 7
11 VCC
10 –INB
+INA 8
9 +INB
GND 1
20 GND
QA 2
19 QB
QA 3
GND 4
LEA 5
LEA 6
18 QB
ADCMP564 17 GND
TOP VIEW
(Not to Scale)
16 LEB
15 LEB
VEE 7
–INA 8
14 VCC
13 –INB
+INA 9
12 +INB
HYSA 10
11 HYSB
Figure 2. ADCMP563 16-Lead QSOP Figure 3. ADCMP564 20-Lead QSOP
GENERAL DESCRIPTION
The ADCMP563/ADCMP564 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of high speed comparators.
A separate programmable hysteresis pin is available on the
ADCMP564.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals
that are fully compatible with ECL 10 K and 10 KH logic
families. The outputs provide sufficient drive current to directly
drive transmission lines terminated in 50 Ω to −2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
The ADCMP563/ADCMP564 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADCMP564 Datasheet, Funktion
ADCMP563/ADCMP564
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
QA 1
16 QB
QA 2
15 QB
GND 3
LEA 4
LEA 5
ADCMP563
TOP VIEW
(Not to Scale)
14 GND
13 LEB
12 LEB
VEE 6
–INA 7
11 VCC
10 –INB
+INA 8
9 +INB
Figure 4. ADCMP563 16-Lead QSOP Pin Configuration
GND 1
20 GND
QA 2
19 QB
QA 3
GND 4
LEA 5
LEA 6
18 QB
ADCMP564 17 GND
TOP VIEW
(Not to Scale)
16 LEB
15 LEB
VEE 7
–INA 8
14 VCC
13 –INB
+INA 9
12 +INB
HYSA 10
11 HYSB
Figure 5. ADCMP564 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP563 ADCMP564 Mnemonic
1 GND
1 2 QA
2 3 QA
3 4 GND
4 5 LEA
5 6 LEA
6 7 VEE
7 8 −INA
8 9 +INA
10 HYSA
11 HYSB
9 12 +INB
10 13 −INB
11 14 VCC
12 15 LEB
Function
Analog Ground.
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
Analog Ground.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to the comparator being placed in the latch mode. LEA must
be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare
mode.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator being placed in the latch mode. LEA
must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
Negative Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A
input must be driven in conjunction with the inverting A input.
Programmable Hysteresis Input.
Programmable Hysteresis Input.
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B
input must be driven in conjunction with the inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
Positive Supply Terminal.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator being placed in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
Rev. A | Page 6 of 16

6 Page









ADCMP564 pdf, datenblatt
ADCMP563/ADCMP564
Propagation delay dispersion is important in critical timing
applications such as ATE, bench instruments, and nuclear
instrumentation. Overdrive dispersion is defined as the varia-
tion in propagation delay as the input overdrive conditions are
changed (Figure 19). For the ADCMP563/ADCMP564, over-
drive dispersion is typically 75 ps as the overdrive is changed
from 100 mV to 1.5 V. This specification applies for both
positive and negative overdrive because the ADCMP563 and
the ADCMP564 have equal delays for positive and negative
going inputs.
1.5V OVERDRIVE
INPUT VOLTAGE
20mV OVERDRIVE
VREF ± VOS
Q OUTPUT
DISPERSION
Figure 19. Propagation Delay Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often useful in a
noisy environment, or where it is not desirable for the compar-
ator to toggle between states when the input signal is at the
switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 20. If the input voltage
approaches the threshold from the negative direction, the
comparator switches from a 0 to a 1 when the input crosses
+VH/2. The new switching threshold becomes −VH/2. The
comparator remains in a 1 state until the threshold −VH/2 is
crossed coming from the positive direction. In this manner,
noise centered on 0 V input does not cause the comparator to
switch states unless it exceeds the region bounded by ±VH/2.
Positive feedback from the output to the input is often used to
produce hysteresis in a comparator (Figure 24). The major
problem with this approach is that the amount of hysteresis
varies with the output logic levels, resulting in a hysteresis that
is not symmetrical around zero.
In the ADCMP564, hysteresis is generated through the
programmable hysteresis pin. A resistor from the HYS pin to
GND creates a current into the part that is used to generate
hysteresis. Hysteresis generated in this manner is independent
of output swing and is symmetrical around the trip point. The
hysteresis versus resistance curve is shown in Figure 21.
A current source can also be used with the HYS pin. The
relationship between the current applied to the HYS pin and the
resulting hysteresis is shown in Figure 17.
–VH
2
0V
+VH
2
INPUT
1
0
OUTPUT
Figure 20. Comparator Hysteresis Transfer Function
160
140
120
100
80
60
40
20
0
50 40 30 20 10
RHYS (k)
0
Figure 21. Comparator Hysteresis vs. RHYS
MINIMUM INPUT SLEW RATE REQUIREMENT
As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input crosses the threshold. This oscillation is due in part to the
high input bandwidth of the comparator and the parasitics of
the package. Analog Devices recommends a slew rate of 1 V/µs
or faster to ensure a clean output transition. If slew rates less
than 1 V/µs are used, hysteresis should be added to reduce the
oscillation.
Rev. A | Page 12 of 16

12 Page





SeitenGesamt 16 Seiten
PDF Download[ ADCMP564 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADCMP561(ADCMP561 / ADCMP562) Dual High Speed PECL ComparatorsAnalog Devices
Analog Devices
ADCMP562(ADCMP561 / ADCMP562) Dual High Speed PECL ComparatorsAnalog Devices
Analog Devices
ADCMP563(ADCMP563 / ADCMP564) Dual High Speed ECL ComparatorsAnalog Devices
Analog Devices
ADCMP564(ADCMP563 / ADCMP564) Dual High Speed ECL ComparatorsAnalog Devices
Analog Devices
ADCMP565Dual Ultrafast Voltage ComparatorAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche