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PDF UPA2752GR Data sheet ( Hoja de datos )
| Número de pieza | UPA2752GR | |
| Descripción | SWITCHING N- AND P-CHANNEL POWER MOS FET | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA2752GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The µPA2752GR is Dual N-Channel MOS Field Effect Transistor
designed for DC/DC converters and power management applications
of notebook computers.
FEATURES
• Dual chip type
• Low on-state resistance
RDS(on)1 = 23.0 mΩ MAX. (VGS = 10 V, ID = 4.0 A)
RDS(on)2 = 35.0 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A)
RDS(on)3 = 41.0 mΩ MAX. (VGS = 4.0 V, ID = 4.0 A)
• Low Ciss: Ciss = 480 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
µPA2752GR
PACKAGE
Power SOP8
PACKAGE DRAWING (Unit: mm)
85
14
5.37 MAX.
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS 30 V
Gate to Source Voltage (VDS = 0 V)
VGSS ±20 V
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit) Note2
Total Power Dissipation (2 unit) Note2
ID(DC)
ID(pulse)
PT
PT
±8.0
±32
1.7
2.0
A
A
W
W
Channel Temperature
Tch 150 °C
Storage Temperature
Single Avalanche Current Note3
Single Avalanche Energy Note3
Tstg –55 to +150 °C
IAS 8 A
EAS 6.4 mJ
EQUIVALENT CIRCUIT
(1/2 Circuit)
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. TA = 25°C, Mounted on ceramic substrate of 2000 mm2 x 2.2 mm
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G15716EJ1V0DS00 (1st edition)
Date Published February 2002 NS CP(K)
Printed in Japan
©
2002
1 page  
µPA2752GR
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
120
100
80
60
40
20
0
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
10
1
R(DVSG(oSn)=Li1m0itVeIDd) (DC)
Power
ID(pulse)
1
Dissipa1tio0n0Lmim1sit0edms
PW
ms
=
100
µs
0.1
Mounted on ceramic substrate
of 2000 mm2 x 2.2 mm
Single Pulse, 1 unit
TA = 25˚C
Single Pulse
0.01
0.1 1
10
VDS - Drain to Source Voltage - V
100
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
Mounted on ceramic
2.4
substrate of
2000 mm2 × 2.2 mm
2 unit
2.0
1 unit
1.6
1.2
0.8
0.4
0
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
Mounted on ceramic substrate
of 2000 mm2 x 2.2 mm
Single Pulse, 1 unit
TA = 25˚C
100
Rth(ch-A) = 73.5˚C/W
10
1
0.1
0.0001
0.001
0.01 0.1
1
PW - Pulse Width - s
10
100 1000
Data Sheet G15716EJ1V0DS
5
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