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DS1500 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS1500
Beschreibung Y2K Watchdog RTC with Nonvolatile Control
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 19 Seiten
DS1500 Datasheet, Funktion
www.maxim-ic.com
GENERAL DESCRIPTION
The DS1500 is a full-function, year 2000-compliant
real-time clock/calendar (RTC) with an alarm,
watchdog timer, power-on reset, battery monitors,
256 bytes of on-board nonvolatile (NV) SRAM, NV
control for backing up an external SRAM, and a
32.768kHz output. User access to all registers within
the DS1500 is accomplished with a byte-wide
interface, as shown in Figure 7. The RTC registers
contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour binary-coded
decimal (BCD) format. Corrections for day of month
and leap year are made automatically.
APPLICATIONS
Remote Systems
Battery-Backed Systems
Telecom Switches
Office Equipment
Consumer Electronics
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS1500YEN -40°C to +85°C 32 TSOP
DS1500WEN -40°C to +85°C 32 TSOP
Selector Guide appears at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
DS1500
Y2K Watchdog RTC with
Nonvolatile Control
FEATURES
§ BCD-Coded Century, Year, Month, Date, Day,
Hours, Minutes, and Seconds with Automatic
Leap-Year Compensation Valid Up to the Year
2100
§ Programmable Watchdog Timer and RTC Alarm
§ Century Register; Y2K-Compliant RTC
§ Automatic Battery Backup and Write Protection
to External SRAM
§ +5V Operation
§ Precision Power-On Reset
§ Power-Control Circuitry Supports System Power-
On from Date/Day/Time Alarm or Key Closure
§ 256 Bytes User NV RAM
§ Auxiliary Battery Input
§ Accuracy Better than ±1 Minute/Month at +25°C
§ Day-of-Week/Date Alarm Register
§ Battery Voltage-Level Indicator Flags
§ Industrial Temperature Range: -40°C to +85°C
PIN CONFIGURATION
TOP VIEW
Dallas
Semiconductor
DS1500
TSOP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 030603






DS1500 Datasheet, Funktion
Figure 4. Burst Mode Timing Waveform
DS1500 Y2KC Watchdog RTC with Nonvolatile Control
A0–A4
13h
PW LOW
PW HIGH
OE, WE, OR CS
DQ0–DQ7
POWER-UP/DOWN CHARACTERISTICS (Figure 5)
PARAMETER
CS, CEI, or WE at VIH Before Power-Fail
SYMBOL
tPF
CONDITIONS
VCCI Fall Time: VPF(MAX) to VPF(MIN)
tF
VCCI Fall Time: VPF(MIN) to VSO
tFB
VCCI Rise Time: VPF(MIN) to VPF(MAX)
tR
VPF to RST High
tREC
MIN TYP MAX UNITS
0 ms
300 ms
10 ms
0 ms
35 200 ms
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Capacitance on All Input Pins
CIN
10 pF
Capacitance on IRQ, PWR, RST, and DQ Pins
CIO
10 pF
AC TEST CONDITIONS
OUTPUT LOAD
(Y) 50pF + 1TTL Gate
(W) 25pF + 1 TTL Gate
INPUT PULSE
LEVELS
0V to 3.0V for
5V operation
TIMING MEASUREMENT
REFERENCE LEVELS
Input: 1.5V
Output: 1.5V
INPUT PULSE RISE
AND FALL TIMES
5ns
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DS1500 pdf, datenblatt
DS1500 Y2KC Watchdog RTC with Nonvolatile Control
DATA RETENTION MODE
The DS1500 is fully accessible and data can be written and read only when VCCI is greater than VPF. However,
when VCCI falls below the power-fail point VPF (point at which write protection occurs) the internal clock registers
and SRAM are blocked from any access. While in the data retention mode, all inputs are don’t cares and outputs
go to a high-Z state, with the exception of VCCO, CEO, and with the possible exception of KS, PWR, SQW, and RST.
CEO is forced high. If VPF is less than VBAT and VBAUX, the device power is switched from VCCI to the greater of VBAT
and VBAUX when VCCI drops below VPF. If VPF is greater than VBAT and VBAUX, the device power and VCCO are
switched from VCCI to the larger of VBAT and VBAUX when VCCI drops below the larger of VBAT and VBAUX. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels (Table 1). If the
square-wave and battery-backup 32kHz functions are enabled, VBAUX always provides power for the square-wave
output, when the device is in battery-backup mode. All control, data, and address signals must be no more than
0.3V above VCCI.
AUXILIARY BATTERY
The VBAUX input is provided to supply power from an auxiliary battery for the DS1500 kickstart and square-wave
output features in the absence of VCCI. This power source must be available to use these auxiliary features when
no VCCI is applied to the device.
This auxiliary battery can be used as the primary backup power source for maintaining the clock/calendar and
external SRAM. This occurs if the VBAT pin is at a lower voltage than VBAUX. If the DS1500 is to be backed-up using
a single battery with the auxiliary features enabled, then VBAUX should be used and connected to VBAT. If VBAUX is
not to be used, it should be grounded.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the level of VCCI. When VCCI falls to the power-fail trip
point, the RST signal (open drain) is pulled low. When VCCI returns to nominal levels, the RST signal continues to be
pulled low for a period of tREC. The power-on reset function is independent of the RTC oscillator and therefore
operational whether or not the oscillator is enabled.
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the RTC
registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time
and date registers are in the binary-coded decimal (BCD) format. Hours are in 24-hour mode. The day-of-week
register increments at midnight. Values that correspond to the day of week are user-defined, but must be
sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in
undefined operation.
READING THE CLOCK
When reading the clock and calendar data, it is possible to access the registers while an update (once per second)
occurs. There are three ways to avoid using invalid time and date data.
The first method uses the transfer enable (TE) bit in the control B register. Transfers are halted when a 0 is written
to the TE bit. Setting TE to 0 halts updates to the user-accessible registers, while allowing the internal registers to
advance. After the registers are read, the TE bit should be written to 1. TE must be kept at 1 for at least 366µs to
ensure a user register update.
The time and date registers can be read and stored in temporary variables. The time and date registers are then
read again, and compared to the first values. If the values do not match, the time and date registers should be read
a third time and compared to the previous values. This should be done until two consecutive reads of the time and
date registers match. The TE bit should always be enabled when using this method for reading the time and date,.
The third method of reading the time and date uses the alarm function. The alarm can be configured to activate
once per second, and the time-of-day alarm-interrupt enable bit (TIE) is enabled. The TE bit should always be
enabled. When the IRQ pin goes active, the time and date information does not change until the next update.
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