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PDF DA82562EX Data sheet ( Hoja de datos )
| Número de pieza | DA82562EX | |
| Descripción | 10/100 Mbps Platform LAN Connect | |
| Fabricantes | Intel | |
| Logotipo |  |
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82562EX 10/100 Mbps Platform LAN
Connect (PLC)
Networking Silicon
Datasheet
Product Features
■ IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
■ IEEE 802.3u Auto-Negotiation support
■ Digital Adaptive Equalization control
■ Link status interrupt capability
■ XOR tree mode support
■ 3-port LED support (speed, link and
activity)
■ 10BASE-T auto-polarity correction
■ LAN Connect interface
■ 82540EM layout compatible
■ Alert on LAN Functionality
■ Diagnostic loopback mode
■ 1:1 transmit transformer ratio support
■ Low power (less than 300 mW in active
transmit mode)
■ Reduced power in “unplugged mode” (less
than 50 mW)
■ Automatic detection of “unplugged mode”
■ 3.3 V device
■ Thin BGA 15mm2 package
■ 82562EZ without Alert on LAN support
available
Revision 1.3
November 2004
1 page  
Networking Silicon — 82562EX
Contents
1.0 Introduction......................................................................................................................... 1
1.1 Overview ............................................................................................................... 1
1.2 Scope .................................................................................................................... 1
1.3 Features ................................................................................................................ 1
1.4 Reference Documents...........................................................................................2
2.0 82562EX Architectural Overview........................................................................................ 3
3.0 82562EX Signal Descriptions............................................................................................. 5
3.1 Signal Type Definitions ......................................................................................... 5
3.2 Twisted Pair Ethernet (TPE) Pins ......................................................................... 5
3.3 External Bias Pins ................................................................................................ 5
3.4 Clock Pins ............................................................................................................ 6
3.5 Platform LAN Connect Interface Pins.................................................................... 6
3.6 LED Pins ..............................................................................................................7
3.7 Miscellaneous Control Pins .................................................................................. 7
3.8 Power and Ground Connections .......................................................................... 8
4.0 Alerting Functionality .......................................................................................................... 9
4.1 4.1 Supported Alerts............................................................................................10
4.1.1 ICH4 Input Signal, INTRUDER# (Cover Tamper) ..................................10
4.1.2 Thermal Event ........................................................................................10
4.1.3 CPU Dead on Arrival ..............................................................................11
4.1.4 Operating System Hang .........................................................................11
4.1.5 BIOS Error Reporting .............................................................................11
4.1.6 Heartbeats..............................................................................................11
4.2 BIOS Requirements ............................................................................................11
4.3 EEPROM Requirements .....................................................................................11
5.0 Physical Layer Interface Functionality..............................................................................13
5.1 100BASE-TX Mode .............................................................................................13
5.1.1 100BASE-TX Transmit Blocks ...............................................................13
5.1.2 100BASE-TX Receive Blocks ................................................................15
5.2 10BASE-T Mode .................................................................................................16
5.2.1 10BASE-T Transmit Blocks ....................................................................16
5.2.2 10BASE-T Receive Blocks .....................................................................16
5.3 Analog References..............................................................................................17
5.4 Dynamic Reduced Power & Auto Plugging Detection.........................................18
5.4.1 Auto Plugging Detection.........................................................................18
5.4.2 Dynamic Reduced Power.......................................................................18
5.4.3 Configuration ..........................................................................................18
5.5 Reset ...................................................................................................................19
5.6 LAN Connect Interface ........................................................................................19
5.6.1 LAN Connect Clock ................................................................................19
5.6.2 LAN Connect Reset................................................................................19
5.7 LED Functionality ...............................................................................................19
Datasheet
v
5 Page 
3.0
3.1
3.2
3.3
Networking Silicon — 82562EX
82562EX Signal Descriptions
Signal Type Definitions
Type
I
O
I/O
MLT
B
DPS
APS
Name
Description
Input
Input pin to the 82562EX.
Output
Output pin from the 82562EX.
Input/Output Multiplexed input and output pin to and from the 82562EX.
Multi-level
analog I/O
Multi-level analog pin used for input and output.
Bias
Bias pin used for ground connection through a resistor or an external voltage
reference.
Digital Power
Supply
Digital power or ground pin for the 82562EX.
Analog Power
Supply
Analog power or ground pin for the 82562EX.
Twisted Pair Ethernet (TPE) Pins
Pin Name
TDP
TDN
RDP
RDN
Type
MLT
MLT
Description
Transmit Differential Pair. The transmit differential pair sends serial bit streams to
the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in
10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-
3). These signals directly interface with the isolation transformer.
Receive Differential Pair. The receive differential pair receive the serial bit stream
from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal
in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-
3). These signals directly interface with an isolation transformer.
External Bias Pins
Pin Name Type
Description
RBIAS10
B
RBIAS100 B
Bias Reference Resistor 10. This pin should be connected to a 619 Ω pull-down
resistor.a
Bias reference Resistor 100. This pin should be connected to a 649 Ω pull-down
resistor.b
a. 619 Ω for RBIAS10 is only a recommended value and should be fine tuned for various designs.
b. 649 Ω for RBIAS100 is only a recommended value and should be fine tuned for various designs.
Datasheet
5
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DA82562EX.PDF ] | |
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