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A54SXxxA Schematic ( PDF Datasheet ) - Actel

Teilenummer A54SXxxA
Beschreibung SX-A Family FPGAs
Hersteller Actel
Logo Actel Logo 




Gesamt 30 Seiten
A54SXxxA Datasheet, Funktion
SX-A Family FPGAs
v5.1
Leading-Edge Performance
• 250 MHz System Performance
• 350 MHz Internal Performance
Specifications
• 12,000 to 108,000 Available System Gates
• Up to 360 User-Programmable I/O Pins
• Up to 2,012 Dedicated Flip-Flops
• 0.22 µ / 0.25 µ CMOS Process Technology
Features
• Hot-Swap Compliant I/Os
• Power-Up/Down Friendly (No Sequencing Required
for Supply Voltages)
• 66 MHz PCI Compliant
• Nonvolatile, Single-Chip Solution
• Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
• 2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
• Devices Support Multiple Temperature Grades
• Configurable Weak-Resistor Pull-Up or Pull-Down
for I/O at Power-Up
• Individual Output Slew Rate Control
• Up to 100% Resource Utilization and 100% Pin
Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
• Boundary-Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and
Design Theft
Table 1 • SX-A Product Profile
Device
A54SX08A
A54SX16A
A54SX32A
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
32,000
48,000
Logic Modules
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
768
512
256
512*
1,452
924
528
990
2,880
1,800
1,080
1,980
Maximum User I/Os
130 180 249
Global Clocks
333
Quadrant Clocks
000
Boundary Scan Testing
Yes Yes Yes
3.3 V / 5 V PCI
Yes Yes Yes
Input Set-Up (External)
0 ns 0 ns 0 ns
Speed Grades
–F, Std, –1, –2
–F, Std, –1, –2, –3 –F, Std, –1, –2, –3
Temperature Grades
C, I, A, M
C, I, A, M
C, I, A, M
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP
208
100, 144
144
208
100, 144
144, 256
208
100, 144, 176
329
144, 256, 484
208, 256
Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
256, 484
208, 256
February 2005
© 2005 Actel Corporation
i
See the Actel website for the latest version of the datasheet.






A54SXxxA Datasheet, Funktion

6 Page









A54SXxxA pdf, datenblatt
SX-A Family FPGAs
4 QCLKBUFS
Quadrant 2
4
5:1 5:1
Quadrant 3
QCLKINT (to array)
Quadrant 0
5:1
QCLKINT (to array)
4
5:1
Quadrant 1
QCLKINT (to array)
Figure 1-9 • SX-A QCLK Architecture
QCLKINT (to array)
OE
From Internal Logic
Clock Network
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
CLKBIBUFI
From Internal Logic
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
QCLKBIBUFI
Figure 1-10 • A54SX72A Routed Clock and QCLK Buffer
1-6 v5.1

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