PDF DS1306 Data sheet ( Hoja de datos )

Número de pieza	DS1306
Descripción	Serial Alarm Real Time Clock RTC
Fabricantes	Dallas Semiconducotr
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No Preview Available ! DS1306 Serial Alarm Real Time Clock (RTC) www.dalsemi.com FEATURES Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 96-byte nonvolatile RAM for data storage Two Time of Day Alarms - programmable on combination of seconds, minutes, hours, and day of the week 1 Hz and 32.768 kHz clock outputs Serial interface supports Motorola Serial Peripheral Interface (SPI) serial data ports or standard 3-wire interface Burst Mode for reading/writing successive addresses in clock/RAM Dual power supply pins for primary and backup power supplies Optional trickle charge output to backup supply 2.0 - 5.5V operation Optional industrial temperature range -40°C to +85°C Available in space-efficient 20-pin TSSOP package Recognized by Underwriters Laboratory ORDERING INFORMATION DS1306 16-Pin DIP DS1306N 16-Pin DIP (Industrial) DS1306E 20-Pin TSSOP DS1306EN 20-Pin TSSOP (Industrial) PIN ASSIGNMENT VCC2 VBAT X1 NC X2 NC INT0 INT1 1 Hz GND 1 20 VCC1 2 19 NC 3 18 32 kHz 4 17 VCCIF 5 16 SDO 6 15 SDI 7 14 SCLK 8 13 NC 9 12 CE 10 11 SERMODE DS1306 20-Pin TSSOP (173 mil) VCC2 VBAT X1 X2 INT0 INT1 1 Hz GND 1 2 3 4 5 6 7 8 16 VCC1 15 32 kHz 14 VCCIF 13 SDO 12 SDI 11 SCLK 10 CE 9 SERMODE DS1306 16-Pin DIP (300 mil) PIN DESCRIPTION VCC1 VCC2 VBAT VCCIF – Primary Power Supply – Backup Power Supply – +3V Battery Input – Interface Logic Power Supply Input GND – Ground X1, X2 – 32.768 kHz Crystal Connection INT0 INT1 SDI SDO CE SCLK SERMODE 1 Hz 32 kHz – Interrupt 0 Output – Interrupt 1 Output – Serial Data In – Serial Data Out – Chip Enable – Serial Clock – Serial Interface Mode - 1 Hz Output - 32.768 kHz Output 1 of 20 070900 1 page DS1306 CLOCK, CALENDAR, AND ALARM The time and calendar information is obtained by reading the appropriate register bytes. The real time clock registers are illustrated in Figure 3. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. Note that some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved. These registers will always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD) format. RTC REGISTERS Figure 3 RTC REGISTERS DS1306 HEX ADDRESS READ WRITE 00H 80H 01H 81H 02H 82H 03H 83H 04H 84H 05H 85H 06H 86H 07H 87H 08H 88H 09H 89H 0AH 8AH 0BH 8BH 0CH 8CH 0DH 8DH 0EH 8EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 10 SEC SEC 0 10 MIN MIN 0 12/2 10 10 HR 4 P/A HOURS 00 0 00 DAY 00 10 DATE DATE 0 0 10 MONTH MONTH 10 YEAR YEAR Alarm 0 M 10 SEC ALARM SEC ALARM M 10 MIN ALARM MIN ALARM M 12/2 10 10 HR 4 P/A HOUR ALARM M 0 0 0 0 DAY ALARM Alarm 1 M 10 SEC ALARM SEC ALARM M 10 MIN ALARM MIN ALARM M 12/2 10 10 HR 4 P/A HOUR ALARM M 0 0 0 0 DAY ALARM RANGE 00-59 00-59 01-12 + P/A 00-23 01-07 1-31 01-12 00-99 00-59 00-59 01-12 + P/A 00-23 01-07 00-59 00-59 01-12 + P/A 00-23 01-07 0FH 10H 11H 12-1FH 8FH 90H 91H 92-9FH CONTROL REGISTER STATUS REGISTER TRICKLE CHARGER REGISTER RESERVED NOTE: Range for alarm registers does not include mask’m’ bits. 5 of 20 5 Page DS1306 ADDRESS AND DATA BYTES Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any transfer requires the address of the byte to specify a write or read to either a RTC or RAM location, followed by 1 or more bytes of data. Data is transferred out of the SDO for a read operation and into the SDI for a write operation (see figures 7 and 8). SPI SINGLE-BYTE WRITE Figure 7 SPI SINGLE-BYTE READ Figure 8 * SCLK can be either polarity. The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of this byte determines if a read or write will take place. If A7 is 0, one or more read cycles will occur. If A7 is 1, one or more write cycles will occur. Data transfers can occur 1 byte at a time or in multiple-byte burst mode. After CE is driven high an address is written to the DS1306. After the address, 1 or more data bytes can be written or read. For a single-byte transfer 1 byte is read or written and then CE is driven low. For a multiple-byte transfer, however, multiple bytes can be read or written to the DS1306 after the address has been written. Each read or write cycle causes the RTC register or RAM address to automatically increment. Incrementing continues until the device is disabled. When the RTC is selected, the address wraps to 00h after incrementing to 1Fh (during a read) and wraps to 80h after incrementing to 9Fh (during a write). When the RAM is selected, the address wraps to 20h after incrementing to 7Fh (during a read) and wraps to A0h after incrementing to FFh (during a write). 11 of 20 11 Page

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