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PDF 80546KF Data sheet ( Hoja de datos )
| Número de pieza | 80546KF | |
| Descripción | 64 Bit Processor | |
| Fabricantes | Intel | |
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64-bit Intel® Xeon™ Processor
MP with up to 8MB L3 Cache
Datasheet
March 2005
Document Number: 306754-001
1 page  
10 Debug Tools Specifications............................................................................................137
10.1 Logic Analyzer Interface (LAI) ...........................................................................137
10.1.1 Mechanical Considerations ..................................................................137
10.1.2 Electrical Considerations......................................................................137
Figures
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On-Die Front Side Bus Termination .................................................................... 17
Phase Lock Loop (PLL) Filter Requirements ...................................................... 20
Processor Load Current vs. Time........................................................................ 30
VCC Static and Transient Tolerance................................................................... 32
VCC and VCACHE Overshoot Example Waveform............................................ 33
Electrical Test Circuit........................................................................................... 42
TCK Clock Waveform.......................................................................................... 43
Differential Clock Waveform................................................................................ 43
Differential Clock Crosspoint Specification.......................................................... 44
Front Side Bus Common Clock Valid Delay Timing Waveform........................... 44
Source Synchronous 2X (Address) Timing Waveform........................................ 45
Source Synchronous 4X (Data) Timing Waveform ............................................. 46
TAP Valid Delay Timing Waveform ..................................................................... 47
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform ... 47
THERMTRIP# Power Down Sequence............................................................... 47
SMBus Timing Waveform.................................................................................... 48
SMBus Valid Delay Timing Waveform ................................................................ 48
Voltage Sequence Timing Requirements............................................................ 49
VIDPWRGD Timing Requirements ..................................................................... 50
FERR#/PBE# Valid Delay Timing ....................................................................... 50
VID Step Timings ................................................................................................ 51
VID Step Times and VCC Waveforms ................................................................ 51
Low-to-High Front Side Bus Receiver Ringback Tolerance ................................ 54
High-to-Low Front Side Bus Receiver Ringback Tolerance ................................ 54
Low-to-High Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 55
High-to-Low Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 56
Maximum Acceptable Overshoot/Undershoot Waveform ................................... 60
Processor Package Assembly Sketch.................................................................61
Processor Package Drawing (Sheet 1 of 2) ........................................................ 63
Processor Package Drawing (Sheet 2 of 2) ........................................................ 64
Processor Topside Markings............................................................................... 67
Processor Bottom-Side Markings........................................................................ 67
Processor Pin-Out Coordinates, Top View.......................................................... 68
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Thermal Profile .. 99
Case Temperature (TCASE) Measurement Location .......................................100
Thermal Monitor 2 Frequency and Voltage Ordering ........................................102
Stop Clock State Machine .................................................................................107
Logical Schematic of SMBus Circuitry ..............................................................110
Passive Processor Thermal Solution (3U and larger) .......................................128
Top Side Board Keep-Out Zones (Part 1) .........................................................129
Top Side Board Keep-Out Zones (Part 2) .........................................................130
Bottom Side Board Keep-Out Zones.................................................................131
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
5
5 Page 
1 Introduction
The 64-bit Intel® Xeon™ processor MP with up to 8MB L3 cache is a 64-bit multi-processor
capable server processor based on improvements to the Intel NetBurst® microarchitecture. It
maintains the tradition of compatibility with IA-32 software and includes features found in the
Intel® Xeon™ processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an
Execution Trace Cache. Hyper Pipelined Technology includes a multi-stage pipeline, allowing the
processor to reach much higher core frequencies. The 667 MHz front side bus is a quad-pumped
bus running off a 166 MHz system clock making 5.3 GB per second data transfer rates possible.
The Execution Trace Cache is a level 1 (L1) cache that stores decoded micro-operations, which
removes the decoder from the main execution path, thereby increasing performance. In addition,
the 64-bit Intel® Xeon™ processor MP with up to 8MB L3 cache includes the Intel® Extended
Memory 64 Technology, providing additional address capability.
In addition, enhanced thermal and power management capabilities are implemented, including
Thermal Monitor, Thermal Monitor 2 (TM2), and Enhanced Intel SpeedStep® technology. Thermal
Monitor and Thermal Monitor 2 provide efficient and effective cooling in high temperature
situations. Enhanced Intel SpeedStep technology allows trade-offs to be made between
performance and power consumption. This may lower average power consumption (in conjunction
with OS support).
The 64-bit Intel® Xeon™ processor MP with up to 8MB L3 cache supports Hyper-Threading
Technology. This feature allows a single, physical processor to function as two logical processors.
While some execution resources such as caches, execution units, and buses are shared, each logical
processor has its own architectural state with its own set of general-purpose registers, control
registers to provide increased system responsiveness in multitasking environments, and headroom
for next generation multi-threaded applications. More information on Hyper-Threading
Technology can be found at http://www.intel.com/technology/hyperthread.
Support for Intel's Execute Disable Bit functionality has been added which can prevent certain
classes of malicious “buffer overflow” attacks when combined with a supporting operating system.
Execute Disable Bit allows the processor to classify areas in memory by where application code
can execute and where it cannot. When a malicious worm attempts to insert code in the buffer, the
processor disables code execution, preventing damage or worm propagation.
Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution,
Advanced Transfer Cache, enhanced floating point and multi-media unit, and Streaming SIMD
Extensions 2 (SSE2). The Advanced Dynamic Execution improves speculative execution and
branch prediction internal to the processor. The Advanced Transfer Cache is a 1 MB on-die level 2
(L2) cache with increased bandwidth. The floating point and multi-media units include 128-bit
wide registers and a separate register for data movement. SSE2 instructions provide highly
efficient double-precision floating point, SIMD integer, and memory management operations. In
addition, Streaming SIMD Extensions 3 (SSE3) instructions have been added to further extend the
capabilities of Intel processor technology. Other processor enhancements include core frequency
improvements and microarchitectural improvements.
The 64-bit Intel® Xeon™ processor MP with up to 8MB L3 cache supports Intel® Extended
Memory 64 Technology (Intel® EM64T) as an enhancement to Intel’s IA-32 architecture. This
enhancement allows the processor to execute operating systems and applications written to take
advantage of the 64-bit extension technology. The processor supports 40-bit addressing, data bus
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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