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PDF DS17285 Data sheet ( Hoja de datos )
| Número de pieza | DS17285 | |
| Descripción | DS17287 / 3V/5V Real-Time Clock | |
| Fabricantes | Dallas | |
| Logotipo |  |
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FEATURES
Incorporates industry standard DS1287 PC clock
plus enhanced features:
§ Y2K compliant
§ +3V or +5V operation
§ SMI recovery stack
§ 64-bit silicon serial number
§ Power-control circuitry supports system
power-on from date/time alarm or key
closure
§ 32kHz output on power-up
§ Crystal select bit allows RTC to operate with
6pF or 12.5pF crystal
§ 114 bytes user NV RAM
§ Auxiliary battery input
§ 2kB additional NV RAM
§ RAM clear input
§ Century register
§ Date alarm register
§ Compatible with existing BIOS for original
DS1287 functions
§ Available as chip (DS17285) or standalone
module with embedded battery and crystal
(DS17287)
§ Timekeeping algorithm includes leap-year
compensation valid up to 2100
§ Underwriters Laboratory (UL) recognized
TYPICAL OPERATING CIRCUIT
DS17285/DS17287
3V/5V Real-Time Clock
PIN ASSIGNMENT
PWR
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 SQW
22 VBAUX
21 RCLR
20 VBAT
19 IRQ
18 KS
17 RD
16 GND
15 WR
14 ALE
13 CS
DS17285 24-Pin DIP
DS17285S 24-Pin SO
PWR
NC
NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 SQW
22 VBAUX
21 RCLR
20 NC
19 IRQ
18 KS
17 RD
16 NC
15 WR
14 ALE
13 CS
DS17287 24-Pin
Encapsulated Package
IRQ
VBAT
RCLR
VBAUX
SQW
VCC
VCC
PWR
X1
X2
NC
ADO
AD1
AD2
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
DS17285E 28-Pin TSOP
KS
RD
GND
WR
ALE
CS
GND
GND
AD7
AD6
NC
AD5
AD4
AD3
1 of 38
050802
1 page  
Figure 1. BLOCK DIAGRAM
DS17285/DS17287
5 of 38
5 Page 
REGISTER C
MSB
BIT 7
IRQF
BIT 6
PF
BIT 5
AF
BIT 4
UF
BIT 3
0
BIT 2
0
DS17285/DS17287
BIT 1
0
LSB
BIT 0
0
IRQF – Interrupt Request Flag. This bit is set to a 1 when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
WF = WIE= 1
KF = KSE= 1
RF = RIE = 1
i.e., IRQF = (PF x PIE) + (AF x AIE) + (UF x UIE) + (WF x WIE) + (KF x KSE) + (RF x RIE)
Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after
Register C is read by the program.
PF – Periodic Interrupt Flag. This is a read-only bit that is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and sets the
IRQF bit. The PF bit is cleared by a software read of Register C.
AF – Alarm Interrupt Flag. A 1 in the AF bit indicates that the current time has matched the alarm
time. If the AIE bit is also a 1, the IRQ pin goes low and a 1 appears in the IRQF bit. A read of Register
C clears AF.
UF – Update Ended Interrupt Flag. This bit is set after each update cycle. When the UIE bit is set to 1,
the 1 in UF causes the IRQF bit to be a 1, which asserts the IRQ pin. UF is cleared by reading Register C.
BIT 3 to BIT 0 – These are unused bits of the status Register C. These bits always read 0 and cannot be
written.
REGISTER D
MSB
BIT 7
VRT
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
VRT – Valid RAM and Time. This bit is a read-only status bit. When VRT = 0, the RTC and RAM data
are questionable and indicates that the lithium energy source has been exhausted and should be replaced.
This bit indicates that status of the VBAT and VBAUX inputs.
BIT 6 to BIT 0 – The remaining bits of Register D are not usable. They cannot be written and, when
read, they always read 0.
11 of 38
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet DS17285.PDF ] | |
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