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DS17885 Schematic ( PDF Datasheet ) - Dallas

Teilenummer DS17885
Beschreibung (DS17886 / DS17887) 3V/5V Real-Time Clock
Hersteller Dallas
Logo Dallas Logo 




Gesamt 30 Seiten
DS17885 Datasheet, Funktion
www.maxim-ic.com
FEATURES
Incorporates industry standard DS1287 PC clock
plus enhanced features:
§ Y2K compliant
§ +3V or +5V operation
§ SMI recovery stack
§ 64-bit silicon serial number
§ Power-control circuitry supports system
power-on from date/time alarm or key
closure
§ 32kHz output on power-up
§ Crystal select bit allows RTC to operate with
6pF or 12.5pF crystal
§ 114 bytes user NV RAM
§ Auxiliary battery input
§ 8kB additional NV RAM
§ RAM clear input
§ Century register
§ Date alarm register
§ Compatible with existing BIOS for original
DS1287 functions
§ Available as chip (DS17885) or standalone
module with embedded battery and crystal
(DS17887)
§ Timekeeping algorithm includes leap-year
compensation valid up to 2100
§ Underwriters Laboratory (UL) recognized
TYPICAL OPERATING CIRCUIT
DS17885/DS17887
3V/5V Real-Time Clock
PIN ASSIGNMENT
PWR
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 SQW
22 VBAUX
21 RCLR
20 VBAT
19 IRQ
18 KS
17 RD
16 GND
15 WR
14 ALE
13 CS
DS17885 24-Pin DIP
DS17885S 24-Pin SO
PWR
NC
NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 SQW
22 VBAUX
21 RCLR
20 NC
19 IRQ
18 KS
17 RD
16 NC
15 WR
14 ALE
13 CS
DS17887 24-Pin
Encapsulated Package
IRQ
VBAT
RCLR
VBAUX
SQW
VCC
VCC
PWR
X1
X2
NC
ADO
AD1
AD2
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
DS17885E 28-Pin TSOP
KS
RD
GND
WR
ALE
CS
GND
GND
AD7
AD6
NC
AD5
AD4
AD3
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DS17885 Datasheet, Funktion
DS17885/DS17887
DS17885 ONLY
X1, X2 – Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS17885 must
be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select
(CS) bit in extended-control register 4B is used to select operation with a 6pF or 12.5pF crystal. The
crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors.
Note: X1 and X2 are very high-impedance nodes. It is recommended that they and the crystal be guard-
ringed with ground and that high frequency signals be kept away from the crystal area.
For more information about crystal selection and crystal layout considerations, refer to Application Note
58, “Crystal Considerations with Dallas Real-Time Clocks.” The DS17885 can also be driven by an
external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
VBAT Battery input for any standard 3V lithium cell or other energy source. Battery voltage must be
held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging
current when used in conjunction with a lithium battery. See “Conditions of Acceptability” at
www.maxim-ic.com/TechSupport/AQ/ntrl.htm.
POWER-DOWN/POWER-UP CONSIDERATIONS
The RTC function continues to operate and all of the RAM, time, calendar, and alarm memory locations
remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the
DS17885/DS17887 and reaches a level of greater than VPF (power-fail trip point), the device becomes
accessible after tREC, provided that the oscillator is running and the oscillator countdown chain is not in
reset (Register A). This time period allows the system to stabilize after power is applied.
The DS17885/DS17887 is available in either a 3V or a 5V device.
The 5V device is fully accessible and data can be written and read only when VCC is greater than 4.5V.
When VCC is below 4.5V, read and writes are inhibited. However, the timekeeping function continues
unaffected by the lower input voltage. As VCC falls below the greater of VBAT and VBAUX, the RAM and
timekeeper are switched over to a lithium battery connected either to the VBAT pin or VBAUX pin.
The 3V device is fully accessible and data can be written or read only when VCC is greater than 2.7V.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT and VBAUX, the
power supply is switched from VCC to the backup supply (the greater of VBAT and VBAUX) when VCC drops
below VPF. If VPF is greater than VBAT and VBAUX, the power supply is switched from VCC to the backup
supply when VCC drops below the larger of VBAT and VBAUX.
When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS , PWR ,
RCLR , and SQW pins, all inputs are ignored and all outputs are in a high-impedance state.
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DS17885 pdf, datenblatt
DS17885/DS17887
NV RAM–RTC
The general-purpose NV RAM bytes are not dedicated to any special function within the
DS17885/DS17887. They can be used by the application program as nonvolatile memory and are fully
available during the update cycle.
The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 real-time
clock registers and 114 bytes of user RAM are accessible. When bank 1 is selected, an additional 4kB of
user RAM are accessible through the extended RAM address and data registers.
INTERRUPT CONTROL
The DS17885/DS17887 includes six separate, fully automatic sources of interrupt for a processor:
1) Alarm Interrupt
2) Periodic Interrupt
3) Update-Ended Interrupt
4) Wake-Up Interrupt
5) Kickstart Interrupt
6) RAM Clear Interrupt
The conditions that generate each of these independent interrupt conditions are described in greater detail
elsewhere in this data sheet. This section describes the overall control of the interrupts.
The application software can select which interrupts, if any, should be used. There are 6 bits including 3
bits in Register B and 3 bits in Extended Register 4B that enable the interrupts. The extended register
locations are described later. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be
initiated when the event occurs. A logic 0 in the interrupt-enable bit prohibits the IRQ pin from being
asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ
is immediately be set at an active level, even though the event initiating the interrupt condition may have
occurred much earlier. As a result, there are cases where the software should clear these earlier generated
interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended
Register 4A. These flag bits are set regardless of the setting of the corresponding enable bit located either
in Register B or in Extended Register 4B. The flag bits can be used in a polling mode without enabling
the corresponding enable bits.
However, care should be taken when using the flag bits of Register C because they are automatically
cleared to 0 immediately after they are read. Double latching is implemented on these bits so that bits that
are set remain stable throughout the read cycle. All bits that were set are cleared when read and new
interrupts that are pending during the read cycle are held until after the cycle is completed. 1 bit, 2 bits, or
3 bits can be set when reading Register C. Each used flag bit should be examined when read to ensure
that no interrupts are lost.
The flag bits in Extended Register 4A are not automatically cleared following a read. Instead, each flag
bit can be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts, the IRQ line is driven low when an interrupt flag
bit is set and its corresponding enable bit is also set. IRQ is held low as long as at least one of the six
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