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Número de pieza | UAA3500HL | |
Descripción | Pager receiver | |
Fabricantes | Philips | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de UAA3500HL (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! INTEGRATED CIRCUITS
DATA SHEET
UAA3500HL
Pager receiver
Preliminary specification
Supersedes data of 1999 Mar 30
File under Integrated Circuits, IC17
2000 Jan 18
1 page Philips Semiconductors
Pager receiver
Preliminary specification
UAA3500HL
PINNING
SYMBOL
CAPI3B
CAPI3A
CAPI2A
CAPI2B
VCC(O)
OUTI
OUTQ
OGND
CAPQ2B
CAPQ2A
CAPQ3A
CAPQ3B
GYRCO2
GYRCO1
GYROUTQ
DRV1
VCC(FE)
VCC(DC)
CAPQ1B
CAPQ1A
LOIN
LOGND
FASTON
VCC(LO)
DRV2
AGCADJ
AGCTAU
RXON
LNAGND1
RFINB
RFINA
LNAGND2
RSET
RSSI
IMINA
IMINB
M1GND
IMOUTA
IMOUTB
M2GND
2000 Jan 18
PIN DESCRIPTION
1 3rd DC filter (I path) external capacitor B (I path)
2 3rd DC filter (I path) external capacitor A (I path)
3 2nd DC filter (I path) external capacitor A (I path)
4 2nd DC filter (I path) external capacitor A (I path)
5 output stage supply voltage B++ (I path)
6 output I and Q signals (I path)
7 output I and Q signals (Q path)
8 output stage ground
9 2nd DC filter external capacitor B (Q path)
10 2nd DC filter external capacitor A (Q path)
11 3rd DC filter external capacitor A (Q path)
12 3rd DC filter external capacitor B (Q path)
13 external resistor to set-up gyrator filter cut-off frequency
14 external resistor to set-up gyrator filter cut-off frequency
15 Q-gyrator output
16 regulator driver (1.8 V)
17 regulated voltage for front-end (1.8 V)
18 input voltage from DC-to-DC converter (2.1 V)
19 1st DC filter external capacitor (Q path)
20 1st DC filter external capacitor (Q path)
21 LO input
22 LO strip ground
23 fast mode enable
24 regulated voltage for LO strip (1.0 V)
25 regulator driver (1.0)
26 AGC loop gain control
27 AGC loop time constant
28 receiver mode enable
29 receiver LNA (Low Noise Amplifier) ground 1
30 LNA input B
31 LNA input A
32 receiver LNA ground 2
33 LNA current setup
34 received signal strength indicator
35 image rejection filter input A
36 image rejection filter input B
37 first mixer ground
38 image rejection filter output A
39 image rejection filter output B
40 second mixers ground
5
5 Page Philips Semiconductors
Pager receiver
Preliminary specification
UAA3500HL
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
LNA
GLNA
NFLNA
IP1LNA
IP3LNA
RF amplifier power gain
RF amplifier noise figure
1 dB input compression point
3rd order intercept point
from RF input to image filter output
fRF = 160 MHz
fRF = 280 MHz
fRF = 930 MHz
from RF input to image filter output
fRF = 160 MHz
fRF = 280 MHz
fRF = 930 MHz
from RF input to image filter output
from RF input to image filter output
First mixer
GFM
NFFM
IP1FM
IP3FM
1st mixer power gain
1st mixer noise figure
1 dB input compression point
3rd order intercept point
Second mixer, PMA, Sallen-Key, 1st DC block and gyrator filter
GvBE
IP3BE
voltage gain
3rd order intercept point
from 2nd mixer input to gyrator output
from 2nd mixer input to gyrator output
1st DC block
fcut-off
cut-off frequency
measured at gyrator output;
FASTON is LOW
fcut-off
cut-off frequency
measured at gyrator output;
FASTON is HIGH
− 20
− 16.2
12.5 14.2
−
−
−
dB
dB
dB
− 1.8 −
− 1.9 −
− 2.2 2.5
− −27 −
−21 −17.6 −
dB
dB
dB
dBm
dBm
−0.5 0
− dB
− 10.2 13 dB
− −22 − dBm
−12.5 −11 −
dBm
42 45
− −59
−
−
dB
dBm
−4
150 400
−
−
Hz
Hz
Note
1. The two tones for intermodulation test would normally be set at 2 and 4 or 4 and 8 channels for type approval tests
i.e 930 and 930.1 or 930.1 and 930.2 MHz.
2000 Jan 18
11
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet UAA3500HL.PDF ] |
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UAA3500HL | Pager receiver | Philips |
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