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PDF CCD5061 Data sheet ( Hoja de datos )
| Número de pieza | CCD5061 | |
| Descripción | 6K x 128 Element / TDI-Time / Delay and Integration Sensor | |
| Fabricantes | Fairchild | |
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PRELIMINARY DATA SHEET
CCD5061
6K x 128 Element
TDI – Time, Delay and Integration Sensor
FEATURES
• 6144 pixels per line
• 128 lines of integration
• 8.75µm x 8.75µm pixel size
• # of TDI stages selectable from 128, 64, 32,
16, 8, 4
• Bi-directional TDI line shifting (shift up or
down)
• 4 outputs—each capable of 20MHz data
rate—80MHz total data rate
• 100% fill factor
• On-chip binning capability
GENERAL DESCRIPTION
The CCD5061 is a 6144 pixel x 128 line,
high speed TDI sensor. The active imaging
area is organized as 6144 vertical columns
and 128 horizontal TDI rows. The array is
set up for bi-directional operation. There are
identical output registers and amplifiers on
both the top and the bottom of the array.
The outputs to be used (either top or
bottom) are user-selectable and controlled
by the vertical clock phasing. In addition,
the exposure level can be controlled by
reducing the number of TDI rows from 128
to 64, 32, 16, 8 or 4. This is also user-
selectable and is accomplished by supplying
the appropriate phasing for the vertical
clocks within each section. For instance, if
64 lines of TDI were required, the vertical
clocks for lines 65-128 would be connected
to a high potential, which would drain these
unused rows out to the opposite side
(unused) of the array to be dumped in the
drain. With four outputs, each running at
20MHz, the CCD5061 can provide a total
data rate of 80MHz enabling the CCD to run
at better than 12KHz line rate. Utilizing
Fairchild Imaging proprietary buried channel
CCD process, the CCD5061 achieves
consistent, superior TDI performance.
The active imaging area is separated from
the four horizontal output registers by 21
isolation rows. These isolation rows are
covered by a metal lightshield to protect
them while charge transfers to the output
registers. Both the active imaging area and
the isolation region utilize 3-phase clocking.
The four horizontal output registers utilize 4-
phase clocking. Special design techniques
have been implemented to maximize charge
transfer efficiency especially at low light
levels. The output amplifier is a 3-stage
source follower configuration. This allows
maximum scale factor (charge to voltage
conversion) and maximum bandwidth.
The CCD5061 is housed in a custom 176
pin (100 mil grid) ceramic PGA package. It
has an AR coated window.
FUNCTIONAL DESCRIPTION
The following functional elements are
illustrated in the block diagram:
Image Sensing Elements: These are
elements of a line of 6144 image sensors
separated by channel stops and covered by
a passivation layer. Incident photons pass
through a transparent polycrystalline silicon
gate structure creating electron hole pairs.
The resulting photoelectrons are collected in
the photosites during the integration period.
The amount of charge accumulated in each
photosite is a linear function of the localized
incident illumination intensity and integration
period.
Transfer Gates: This gate is a structure
adjacent to the row of image sensor
elements. The charge packets accumulated
in the photosites are transferred in parallel
via the transfer gate to the transport shift
1801 McCarthy Blvd., Milpitas CA 95035; (800) 325-6975; Fax (408) 435-7352; www.fairchildimaging.com Page 1 of 17
1 page  
PRELIMINARY DATA SHEET
CCD5061
6K x 128 Element
TDI – Time, Delay and Integration Sensor
TEST CONDITIONS
All testing performed at 25ºC (nominal)
with horizontal clock frequency of 20MHz
per output and vertical clock frequency of
12KHz.
CCD HANDLING PRECAUTIONS TO
PREVENT ESD DAMAGE
By their very nature, CCDs are very sensitive to
electro-static discharge (ESD) damage. Special
ESD-control equipment and personnel training
are mandatory, particularly when installing or
removing the CCD from a camera system. See
Fairchild Imaging application note “Prevention of
ESD Damage in CCD Image Sensors” for
details. Key points:
Use ESD-safe workbench surfaces. Cover
metallic workbench surfaces with ESD-safe
grounded mats. Remove non-ESD-safe
materials (paper, tools with plastic handles,
etc.) from work area.
Use wrist straps or equivalent (~1MΏ to
ground), ESD-safe lab coat or equivalent
(buttoned—not open), and ESD-safe gloves
or finger cots. Test wrist strap before
handling CCDs.
Relative humidity must be 40% min.; >50%
recommended.
Use ionizing air blowers; type: AC (not pulsed
DC), balance ≤±20V max., ≤±10V
recommended. Performance spec at work
area: voltage decay from 1000V to 100V in
<10 seconds. Measure this periodically; air
ionizers require maintenance.
Allow devices to slowly discharge in the
ionized air stream when removing devices
from their 1st-level container, and when
removing devices from test sockets.
The receiving socket and associated circuitry
must be adequately grounded.
Store CCDs with all pins shorted together by
shorting bars, conductive foam, or the
equivalent.
ESD damage invalidates the warranty.
1801 McCarthy Blvd., Milpitas CA 95035; (800) 325-6975; Fax (408) 435-7352; www.fairchildimaging.com Page 5 of 17
5 Page 
PRELIMINARY DATA SHEET
CCD5061
6K x 128 Element
TDI – Time, Delay and Integration Sensor
Vertical-to-Horizontal Clock Timing (1x1 full-resolution mode)
VHS1
VHS2
VHS3
H1
H2
H3
H4
FOG (φOG)
RG (φR)
VOUT
H1-Trilevel-high must start
within this time period
H1 Trilevel high
optional – FOG may be clocked here
pixel #1536 (line #n)
≥4 horiz. overscan cells
(≥16 recommended)
≥0.000µs
≥0.7µs each (≥1.0µs preferred)
pixel #1 (line #n+1)
1801 McCarthy Blvd., Milpitas CA 95035; (800) 325-6975; Fax (408) 435-7352; www.fairchildimaging.com Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CCD5061.PDF ] | |
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