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PDF ACS8510REV Data sheet ( Hoja de datos )
| Número de pieza | ACS8510REV | |
| Descripción | Synchronous Equipment Timing Source for SONET or SDH Network Elements | |
| Fabricantes | Semtech | |
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ADVANCED COMMUNICATIONS
ACS8510 Rev2.1 SETS
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
Description
Features
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
Block Diagram
Figure 1. Simple Block Diagram
•Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
•Meets AT&T, ITU-T, ETSI and Telcordia
specifications
•Accepts 14 individual input reference clocks
•Generates 11 output clocks
•Supports Free-run, Locked and Holdover
modes of operation
•Robust input clock source quality monitoring on
all inputs
•Automatic ‘hit-less’ source switchover on loss
of input
•Phase build out for output clock phase
continuity during input switchover and mode
transitions
•Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EPROM
•Programmable wander and jitter tracking
attenuation 0.1 Hz to 20 Hz
•Support for Master/Slave device configuration
alignment and hot/standby redundancy
•IEEE 1149.1 JTAG Boundary Scan
•Single +3.3 V operation, +5 V I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
•Available in 100 pin LQFP package
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
2 x AMI
10 x TTL
2 x PECL/LVDS
Programmable;
64/8kHz
2kHz
4kHz
N x 8kHz
1.544/2.048MHz
6.48MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
TCK
TDI
TMS
TRST
TDO
Input
Ports
14xSEC
TOUT4
selector
Monitors
Divider
Digital
PFD Loop
Filter
DPLL/Freq. Synthesis
DTO
MFrSync
IEEE
1149.1
JTAG
TOUT0
selector
Divider
Digital
PFD Loop DTO
Filter
DPLL/Freq. Synthesis
Chip Clock
Generator
Priority
Table
Register
Set
Microprocessor
Port
APLL
Frequency
Dividers
Output
Ports
9xSEC
FrSync
MFrSync
1 x AMI
6 x TTL
2 x PECL/LVDS
Programmable:
64/8kHz
1.544/2.048MHz
3.088/4.096MHz
6.176/8.182MHz
12.352/16.384MHz
6.48MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
311.04MHz
2kHz MFrSync
8kHz FrSync
TCXO (*OCXO)
Revision 2.00/September 2003 Semtech Corp.
www.semtech.com
1 page  
ADVANCED COMMUNICATIONS
Pin Diagram
Figure 2. ACS8510 Pin Diagram
ACS8510 Rev2.1 SETS
FINAL
1 AGND
2 TRST
3 IC
4 NC
5 AGND
6 VA1+
7 TMS
8 INTREQ
9 TCK
10 REFCLK
11 DGND
12 VD+
13 VD+
1
14 DGND
15 DGND
16 VD+
17 NC
18 SRCSW
19 VA2+
20 AGND
21 TDO
22 IC
23 TDI
24 I1
25 I2
26 VAMI+
ACS8510
27 TO8NEG
28 TO8POS
SDH/SONET SETS
29 GND_AMI
30 FrSync
31 MFrSync
Rev 2.1
32 GND_DIFF
33 VDD_DIFF
34 TO6POS
35 TO6NEG
36 TO7POS
37 TO7NEG
38 GND_DIFF
39 VDD_DIFF
40 I5POS
41 I5NEG
42 I6POS
43 I6NEG
44 VDD5
45 SYNC2K
46 I3
47 I4
48 I7
49 DGND
50 VDD
NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float.
100 SONSDHB
99 MSTSLVB
98 IC
97 IC
96 IC
95 TO9
94 TO5
93 TO4
92 DGND
91 VDD
90 TO3
89 TO2
88 TO1
87 DGND
86 VDD
85 VDD
84 DGND
83 AD0
82 AD1
81 AD2
80 AD3
79 AD4
78 AD5
77 AD6
76 AD7
75 RDY
74 PORB
73 ALE
72 RDB
71 WRB
70 CSB
69 A0
68 A1
67 A2
66 A3
65 A4
64 A5
63 A6
62 DGND
61 VDD
60 UPSEL0
59 UPSEL1
58 UPSEL2
57 I14
56 I13
55 I12
54 I11
53 I10
52 I9
51 I8
Revision 2.00/September 2003 Semtech Corp.
5
www.semtech.com
5 Page 
ACS8510 Rev2.1 SETS
ADVANCED COMMUNICATIONS
FINAL
Input Reference Clock Ports
Table 4 gives details of the input reference
ports, showing the input technologies and the
range of frequencies supported on each port;
the default spot frequencies and default
priorities assigned to each port on power-up or
by reset are also shown. Note that SDH and
SONET networks use different default
frequencies; the network type is pin-selectable
(using the SONSDHB pin). Specific frequencies
and priorities are set by configuration.
Although each input port is shown as belonging
to one of the types, TIN1, TIN2 or TIN3, they are
fully interchangeable as long as the selected
speed is within the maximum operating speed
of the input port technology.
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
100). Specific frequencies and priorities are set
by configuration.
TTL ports (compatible also with CMOS signals)
support clock speeds up to 100 MHz, with the
highest spot frequency being 77.76 MHz. The
actual spot frequencies supported are:
• 2 kHz
• 4 kHz
• 8 kHz (and N x 8 kHz)
• 1.544 MHz (SONET)/2.048 MHz (SDH)
• 6.48 MHz,
• 19.44 MHz,
• 25.92 MHz,
• 38.88 MHz,
• 51.84 MHz,
• 77.76 MHz.
The frequency selection is programmed via the
cnfg_ref_source_frequency register. The
internal DPLL will normally lock to the selected
input at the frequency of the input, eg. 19.44
MHz will lock the DPLL phase comparisons at
19.44 MHz. It is, however, possible to utilise
an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase
comparisons in the DPLL. This pre-divider can
be used in one of 2 ways:
1. Any of the supported spot frequencies can be divided to
8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate
cnfg_ref_source_frequency register location. For good jitter
tolerance for all frequencies and for operation at
19.44 MHz and above, use lock8K. It is possible to choose
which edge of the 8kHz input to lock to, by setting the
appropriate bit of the cnfg_control1 register.
2. Any multiple of 8 kHz between 1544 kHz to 100 MHz
can be supported by using the ‘DivN’ feature (bit 7 of the
cnfg_ref_source_frequency register). Any reference input
can be set to use DivN independently of the frequencies
and configurations of the other inputs.
Any reference input with the DivN bit set in the
cnfg_ref_source_frequency register will employ
the internal pre-divider prior to the DPLL locking.
The cnfg_freq_divn register contains the divider
ratio N where the reference input will get divided
by (N+1) where 0<N<214-1.
The
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
input frequency. When using the DivN feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the ‘lock8k’ bit high (bit
6 in cnfg_ref_source_frequency register). Any
input set to DivN must have the frequency
monitors disabled (If the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the DivN feature, only one N can be
programmed, hence all inputs using the DivN
feature must require the same division to get
to 8 kHz.
Revision 2.00/September 2003 Semtech Corp.
11
www.semtech.com
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