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DS1236A Schematic ( PDF Datasheet ) - DALLAS

Teilenummer DS1236A
Beschreibung MicroManager Chip
Hersteller DALLAS
Logo DALLAS Logo 




Gesamt 20 Seiten
DS1236A Datasheet, Funktion
www.dalsemi.com
DS1236A
MicroManager Chip
FEATURES
Holds microprocessor in check during power
transients
Halts and restarts an out-of-control
microprocessor
Monitors pushbutton for external override
Warns microprocessor of an impending power
failure
Converts CMOS SRAM into nonvolatile
memory
Unconditionally write protects memory when
power supply is out of tolerance
Consumes less than 100 nA of battery current
at 25°C
Controls external power switch for high
current applications
Accurate 10% power supply monitoring
Optional 5% power supply monitoring
designated DS1236A-5
Provides orderly shutdown in nonvolatile
microprocessor applications
Supplies necessary control for low-power
“stop mode” in battery operated hand-held
applications
Standard 16-pin DIP or space-saving 16-pin
SOIC
Optional industrial temperature range -40°C
to +85°C
PIN ASSIGNMENT
VBAT 1 16 RST
VCCO 2 15 RST
VCC
GND
PF
PF
WC/SC
RC
3
4
5
6
7
8
14 PBRST
13 CEI
VBAT
VCCO
12 CEO
VCC
11 ST
10 NMI
GND
PF
PF
9 IN
WC/SC
RC
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
RST
RST
PBRST
CEI
CEO
ST
NMI
IN
16-Pin DIP (300-mil)
See Mech. Drawings Section
16-Pin SOIC (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
VBAT
VCCO
VCC
GND
- +3-Volt Battery Input
- Switched SRAM Supply Output
- +5-Volt Power Supply Input
- Ground
PF - Power-Fail (Active High)
PF - Power-Fail (Active Low)
WC/ SC
- Wake-Up Control (Sleep)
RC - Reset Control
IN - Early Warning Input
NMI - Non-Maskable Interrupt
ST - Strobe Input
CEO - Chip Enable Output
CEI - Chip Enable Input
PBRST
- Pushbutton Reset Input
RST - Reset Output (Active Low)
RST - Reset Output (Active High)
DESCRIPTION
The DS1236A MicroManager Chip provides all the necessary functions for power supply monitoring,
reset control, and memory backup in microprocessor-based systems. A precise internal voltage reference
and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1236A also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset
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DS1236A Datasheet, Funktion
DS1236A
If the IN pin is connected to VCCO, the NMI output will pulse low as VCC decays to VCCTP in the NMOS
mode (RC=0). In the CMOS mode (RC=VCCO) the power-down of VCC out of tolerance at VCCTP will not
produce a pulse on the NMI pin. Given that any NMI pulse has been completed by the time VCC decays
to VCCTP, the NMI pin will remain high. The NMI voltage will follow VCC down until VCC decays to
VBAT. Once VCC decays to VBAT, the NMI pin will either remain at VOHL or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236A provides all of the necessary functions required to battery back a static RAM. First, a
switch is provided to direct SRAM power from the incoming 5-volt supply (VCC) or from an external
battery (VBAT), whichever is greater. This switched supply (VCCO) can also be used to battery back a
CMOS microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of VCC or to within 0.7
volts of VBAT. This write protection mechanism occurs as VCC falls below VCCTP as specified. If CEI is
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high or
the period tCE expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of VCC-fail detection, CEO will be
unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application. The
DS1236A unlike the DS1236 can be operated without a battery. In this method of operation the VBAT, pin
1, must be grounded. In general, it would also be expected to have the RC, pin 8, grounded (NMOS
mode) since no battery backup is available.
FRESHNESS SEAL
In order to conserve battery capacity during initial construction of an end system, the DS1236A provides
a freshness seal that electrically disconnects the battery. This means that upon battery attach, the VCCO
output will remain inactive until VCC is applied. This prevents VCCO from powering other devices when
the battery is first attached, and VCC is not present. Once VCC is applied, the freshness seal is broken and
cannot be invoked again without subsequent removal and reattachment of the battery.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236A may not be large enough to support the required load through
VCCO with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gate
external power switching devices. As shown in Figure 8, power to the load is switched from VCC to
battery on power-down, and from battery to VCC on power-up. The DS1336 is designed to use the PF
output to switch between VBAT and VCC It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage VBAT, allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236A supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST, RST , and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery-operated processor applications.
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DS1236A pdf, datenblatt
DS1236A
grounded (NMOS mode). If the RC pin is tied high, the RST and RST pins will remain inactive during
power-down in a sleep mode. Removal of the sleep mode by the PBRST input is not affected by the IN
pin threshold at VTP when the RC pin is tied high (CMOS mode). Subsequent power-up of the VCC supply
with the RC pin tied high will activate the RST and RST outputs as the main supply rises above VBAT. A
high-to-low transition on the WC/ SC pin must follow a high-to-low transition on the ST pin by tWC to
invoke a Sleep mode for the DS1236A.
POWER SWITCHING Figure 8
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