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CA3082 Schematic ( PDF Datasheet ) - Intersil

Teilenummer CA3082
Beschreibung General Purpose High Current NPN Transistor Arrays
Hersteller Intersil
Logo Intersil Logo 




Gesamt 6 Seiten
CA3082 Datasheet, Funktion
Data Sheet
General Purpose High Current NPN
Transistor Arrays
CA3081 and CA3082 consist of seven high current (to
100mA) silicon NPN transistors on a common monolithic
substrate. The CA3081 is connected in a common emitter
configuration and the CA3082 is connected in a common
collector configuration.
The CA3081 and CA3082 are capable of directly driving
seven segment displays, and light emitting diode (LED)
displays. These types are also well suited for a variety of
other drive applications, including relay control and thyristor
firing.
Ordering Information
PART NUMBER
(BRAND)
CA3081
CA3081F
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld CERDIP
PKG.
NO.
E16.3
F16.3
CA3081M
(3081)
CA3082
CA3082M
(3082)
CA3082M96
(3082)
-55 to 125 16 Ld SOIC
M16.15
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld SOIC
E16.3
M16.15
-55 to 125 16 Ld SOIC Tape M16.15
and Reel
CA3081, CA3082
November 1999
File Number 480.5
Features
• CA3081 - Common Emitter Array
• CA3082 - Common Collector Array
• Directly Drive Seven Segment Incandescent Displays and
Light Emitting Diode (LED) Display
• 7 Transistors Permit a Wide Range of Applications in
Either a Common Emitter (CA3081) or Common Collector
(CA3082) Configuration
• High IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Max)
• Low VCESAT (at 50mA) . . . . . . . . . . . . . . . . . . 0.4V (Typ)
Applications
• Drivers for
- Incandescent Display Devices
- LED Displays
• Relay Control
• Thyristor Firing
Pinouts
CA3081
COMMON EMITTER CONFIGURATION
(PDIP, CERDIP, SOIC)
TOP VIEW
1
2
3
4
SUBSTRATE 5
6
7
8
16
15
14
13
12
11
10
9
CA3082
COMMON COLLECTOR CONFIGURATION
(PDIP, SOIC)
TOP VIEW
1
2
3
4
SUBSTRATE 5
6
7
8
16
15
14
13
12
11
10
9
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999






CA3082 Datasheet, Funktion
CA3081, CA3082
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A- -D-
E
-B-
bbb S C A - B S D S
c1 LEAD FINISH
BASE
METAL
(c)
b1
MM
(b)
SECTION A-A
BASE
PLANE
SEATING
PLANE
S1
b2
b
D
AA
e
Q
-C- A
L
eA/2
α
eA
c
ccc M C A - B S D S
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
- 0.200 - 5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D - 0.840 - 21.34 5
E
0.220
0.310
5.59
7.87
5
e 0.100 BSC
2.54 BSC
-
eA 0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1 0.005 - 0.13 - 7
α
90o 105o 90o 105o
-
aaa
- 0.015 - 0.38
-
bbb
- 0.030 - 0.76
-
ccc
- 0.010 - 0.25
-
M
-
0.0015
-
0.038
2, 3
N 16
16 8
Rev. 0 4/94
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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ASIA
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Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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