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DIR1701 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer DIR1701
Beschreibung DIGITAL AUDIO INTERFACE RECEIVER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 19 Seiten
DIR1701 Datasheet, Funktion
DIR1701
SLAS331 – APRIL 2001
DIGITAL AUDIO INTERFACE RECEIVER
FEATURES
D Standard Digital Audio Interface Receiver
(EIAJ1201)
D Sampling Rate: 32/44.1/48/88.2/96 kHz
D Recover 128 / 256 / 384 / 512 fs System Clock
D Very Low Jitter System Clock Output (80ps
Typically)
D On-Chip Master Clock Oscillator, Only an
External 12.000 MHz or 16.000 MHz Crystal Is
Required
D Selectable Output PCM Audio Data Format
D Output User Bit Data, Flag Signals, and
Channel Status Data With Block Start Signal
D Single + 3.3-V Power Supply
D Package: 28 SSOP
APPLICATIONS
D AV Receiver
D MD Player
D DAC Unit
DESCRIPTION
The DIR1701 is a digital audio interface receiver
(DIR) which receives and decodes audio data up
to 96 kHz according to the AES/EBU, IEC958,
S/PDIF, and EIAJCP340/1201 consumer and
professional format interface standards. The
DIR1701 demultiplexes the channel status bit and
user bit directly to serial output pins, and has
dedicated output pins for the most important
channel status bits.
The significant advantages of the DIR1701 are
96 kHz sampling rate capability and Low-jitter
clock recovery by the Sampling Period Adaptive
Controlled Tracking (SpAct) system. Input signal
is reclocked with the patented Sampling period
Adaptive controlled tracking system for maximum
quality. These two features are required for recent
consumer and professional audio instruments, in
which the DIR has an interface to any kind of
delta-sigma type ADC/DAC with 96 kHz sampling
rate.
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct and Burr-Brown are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright 2001, Texas Instruments Incorporated
1






DIR1701 Datasheet, Funktion
DIR1701
SLAS331 APRIL 2001
basic operation theory
The DIR1701 has two PLLs, PLL1 and PLL2. The SpAct (Sampling Period Adaptive Controlled Tracking)
system is a newly developed clock recovery architecture, giving very low jitter clock from S/PDIF data input. The
DIR1701 requires a system clock input for operation of SpAct; internal PLL1 provides a 100 MHz execution
clock. The system clock can be obtained by either connecting a suitable crystal resonator at the XTI/XTO pins
or applying an external clock input at the XTI pin as shown in Figure 1. Internal PLL2 generates the system clock
SCKO by using the output signal of the SpAct frequency estimator.
When the S/PDIF input signal ceases, SCKO holds the latest tracked frequency. Also, the DIR1701 indicates
the unlocked state by a HIGH level output at the UNLOCK pin. When the S/PDIF signal restarts, the PLL will
lock in around 1ms with very low jitter, using the SpAct estimator. Then the DIR1701 indicates the locked status
by a LOW level output at the UNLOCK pin. In this status, the BRATE pins indicate the actual bit rate of the
incoming S/PDIF signal.
C 1 Crystal
External Clock
XTI XTAL
R1 OSC
CIR
XTO
C2
R1 = 1 M,
C1, C2 = 10 TO 33 pF
DIR1701
Crystal Resonator Connection
Open
Figure 1. System Clock Connections
XTI
XTO
XTAL
OSC
CIR
DIR1701
External Clock Input
system clock output
The primary function of the DIR1701 is to recover audio data and a low jitter clock from a digital audio
transmission line. The clocks that can be generated are SCKO (128/256/384/512 fS, shown in Table 1), BCKO
(64 fS), and LRCKO (1 fS). SCKO is the output of the voltage controlled oscillator (VCO) in an analog PLL. The
PLL function consists of a VCO, phase and frequency detector, and a external second-order loop filter. The
closed-loop transfer function, which specifies the PLL jitter attenuation characteristics, is shown in Figure 2.
The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins
BFRAME or CSBIT as shown in Table 2. A 12 MHz crystal resonator can be used for 128fS (CSBIT), 256fS
(OPEN) and 384fS (BFRAME). And a 16 MHz crystal resonator is used for 512fS (BFRAME). The system clock
frequency can be set by control data at SCF0, SCF1 pin (shown in Table 3); this data must be stable before reset
is applied.
Table 4 shows the state of the system and the condition of audio clocks and flags. Required accuracy of system
clock by either crystal resonator or external clock input is ±500 ppm.
Table 1. Generated System Clock (SCKO) Frequencies
SAMPLING
RATE
32 kHz
44.1 kHz
48 kHz
88.2kHz
96 kHz
128 fS
4.096 MHz
5.6448 MHz
6.144 MHz
11.2896 MHz
12.288 MHz
256 fS
8.192 MHz
11.2896 MHz
12.288 MHz
22.5792 MHz
24.576 MHz
384 fS
12.288 MHz
16.9344 MHz
18.432 MHz
33.8688 MHz
36.864 MHz
512 fS
16.384 MHz
22.5792 MHz
24.576 MHz
45.1584 MHz
49.152 MHz
6 www.ti.com

6 Page









DIR1701 pdf, datenblatt
DIR1701
SLAS331 APRIL 2001
PCM audio interface (continued)
Standard Data Format; LChannel = HIGH, RChannel = LOW
LRCKO
LChannel
1/fS
BCKO
Right Justified
Audio Data Word = 16Bit
DOUT 14 15 16
Right Justified
Audio Data Word = 24Bit
DOUT 22 23 24
Left Justified
Audio Data Word = 24Bit
DOUT
12
MSB
12
MSB
15 16
LSB
12
MSB
23 24
LSB
23 24
LSB
12
MSB
RChannel
12
MSB
15 16
LSB
12
MSB
23 24
LSB
23 24
LSB
IIS Data Format; LChannel = LOW, RChannel = HIGH
LRCKO
BCKO
LChannel
1/fS
RChannel
Audio Data Word = 24Bit
DOUT
12
MSB
23 24
LSB
12
MSB
Figure 7. Audio Data Output Format
23 24
LSB
1
12 www.ti.com

12 Page





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