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DG528 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer DG528
Beschreibung Analog CMOS Latchable Multiplexers
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 16 Seiten
DG528 Datasheet, Funktion
April 1999
Semiconductor
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DG526, DG527,
DG528, DG529
Analog CMOS
Latchable Multiplexers
Features
Description
• Direct RESET
• TTL and CMOS Compatible Address and Enable
Inputs
• Maximum Power Supply Rating . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Switching
• Alternate Source
Applications
• Data Acquisition Systems
• Communication Systems
• Automatic Test Equipment
• Microprocessor Controlled Systemd
The DG526, DG527, DG528, and DG529 are CMOS
Monolithic 16-Channel/Dual 4-Channel Analog Multiplexers.
Each device has on-chip address and control latches to sim-
plify design in microprocessor based applications. The DG526
uses 4 address lines to control its 16 channels; the DG527,
DG528 both use 3 address lines to control their 8 channels;
and the DG529 uses 2 address lines to control its 4 channels.
The enable pin is used to enable the address latches during
the WR pulse. It can be hard wired to the logic supply if one of
the channels will always be used (except during a reset) or it
can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used to clear all latches regardless of
the state of any other latch or control line. The WR pin is used
to transfer the state of the address control lines to their
latches, except during a reset or when EN is low.
A channel in the ON state conducts signals equally well in
both directions. In the OFF state each channel blocks volt-
ages up to the supply rails. The address inputs, WR, RS and
the enable input are TTL and CMOS compatible over the full
specified operation temperature range.
Part Number Information
PART
NUMBER
DG526AK
DG526AK/883B
DG526BK
DG526BY
DG526CJ
DG526CK
DG526CY
DG527AK
DG527AK/883B
DG527BK
DG527BY
DG527CJ
DG527CK
DG527CY
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
-25 to 85 28 Ld CERDIP
-25 to 85 28 Ld SOIC
0 to 70 28 Ld PDIP
0 to 70 28 Ld CERDIP
0 to 70 28 Ld SOIC
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
-25 to 85 28 Ld CERDIP
-25 to 85 28 Ld SOIC
0 to 70 28 Ld PDIP
0 to 70 28 Ld CERDIP
0 to 70 28 Ld SOIC
PKG. NO.
F28.6
F28.6
F28.6
M28.3
E28.6
F28.6
M28.3
F28.6
F28.6
F28.6
M28.3
E28.6
F28.6
M28.3
PART
NUMBER
DG528AK
DG528AK/883B
DG528BK
DG528BY
DG528CJ
DG528CK
DG528CY
DG529AK
DG529AK/883B
DG529BK
DG529BY
DG529CJ
DG529CK
DG529CY
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 18 Ld CERDIP
-55 to 125 18 Ld CERDIP
-25 to 85 18 Ld CERDIP
-25 to 85 18 Ld SOIC
0 to 70 18 Ld PDIP
0 to 70 18 Ld CERDIP
0 to 70 18 Ld SOIC
-55 to 125 18 Ld CERDIP
-55 to 125 18 Ld CERDIP
-25 to 85 18 Ld CERDIP
-25 to 85 18 Ld SOIC
0 to 70 18 Ld PDIP
0 to 70 18 Ld CERDIP
0 to 70 18 Ld SOIC
PKG. NO.
F18.3
F18.3
F18.3
M18.3
E18.3
F18.3
M18.3
F18.3
F18.3
F18.3
M18.3
E18.3
F18.3
M18.3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
12-1
File Number 3139.2






DG528 Datasheet, Funktion
DG526, DG527, DG528, DG529
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC,
Unless Otherwise Specified (Continued)
A SUFFIX
B AND C SUFFIX
PARAMETER
(NOTE 6)
TEST CONDITIONS
Drain OFF
Capacitance,
CD(OFF)T
DG526 VD = 0V
DG527
DG528
VEN = 0V,
f = 140kHz
DG529
Charge
Injection, Q
DG526, See Figure 8
DG527
(NOTE 2)
MIN TYP MAX
- 65 -
- 35 -
- 25 -
- 12 -
-6-
(NOTE 2)
MIN TYP MAX UNITS
- 65 - pF
- 35 - pF
- 25 - pF
- 12 - pF
- 6 - pC
DG528,
DG529
INPUT
Address Input
Current, Input
Voltage High,
IAH
Address Input
Current, Input
Voltage Low,
IAL
SWITCH
DG526, VA = 2.4V
DG527
VA = 15V
DG528, VA = 2.4V
DG529
VA = 15V
DG526 VEN = 2.4V
DG527
VEN = 0V
DG528 VEN = 2.4V
DG529
VEN = 0V
All VA = 0V,
RS = 0V,
WR = 0V
- 4 - - 4 - pC
-10 0.02
- -10 0.02
- µA
- 0.02 10 - 0.02 10 µA
-10 -0.002 - -10 -0.002 - µA
-
0.006
10
-
0.006 10 µA
-10 0.01
- -10 0.01
- µA
-10 0.01
- -10 0.01
- µA
-10 -0.002 - -10 -0.002 - µA
-10 -0.002 - -10 -0.002 - µA
Analog Signal Range,
VANALOG
(Note 7)
-15 - +15 -15 - +15 V
Drain Source ON
Resistance, rDS(ON)
VD = ±10V, VAL = 0.8V, VAH = 2.4V,
IL = -200µA
Sequence Each Switch ON
-
270 400 -
270 450
Greatest Change in Drain -10V VS 10V
- 6 - - 6 -%
Source ON Resistance
Between Channels,
DrDS(ON) = rDS(ON)MAX - rDS(ON)MIN
rDS(ON)
rDS(ON)AVG.
Source OFF
Leakage
Current,
IS(OFF)
DG526, VEN = 0V
DG527
DG528,
DG529
VS = ±10V,
VD = +10V
VS = ±10V,
VD = +10V
-1 0.02
-1 -0.005
1
1
- 0.02 -
-5 -0.005 5
nA
nA
Drain OFF
Leakage
Current,
ID(OFF)
DG526 VEN = 0V
DG527
VS = ±10V,
VD = +10V
VS = ±10V,
VD = +10V
-10 0.2 10 - 0.2 - nA
-5 0.2 5 - 0.2 - nA
DG528
VS = ±10V,
VD = +10V
-10 -0.015 10 -20 0.015 20 nA
DG529
VS = ±10V,
VD = +10V
-10 -0.008 10 -20 0.008 20 nA
Drain ON
DG526 Sequence Each VD = VS(ALL) =
-10
0.2
10 -
0.2
- nA
Leakage
Switch On
±10V
Current, ID(ON) DG527
VAL = 0.8V and
VAH = 2.4V
(Note 5)
VD = VS(ALL) =
±10V
-5
0.2
5-
0.2
- nA
12-6

6 Page









DG528 pdf, datenblatt
DG526, DG527, DG528, DG529
Truth Tables
DG526
Latching
A3 A2 A1 A0 EN WR RS ON SWITCH
XXXXX
1 Maintains
Previous
Switch State
Reset
X X X X X X 0 None
(Latches
Cleared)
Trans-
XXXX0 0 1
parent
Operation 0 0 0 0 1 0 1
0001101
None
1
2
0010101
3
0011101
4
0100101
5
0101101
6
0110101
7
0111101
8
1000101
9
1001101
10
1010101
11
1011101
12
1100101
13
1101101
14
1110101
15
1111101
16
Logic “0” = VAL, VENL 0.8V
DG527
Latching
A2 A1 A0 EN WR RS ON SWITCH
XXXX
1 Maintains
Previous
Switch State
Reset
X X X X X 0 None
(Latches
Cleared)
Trans-
XXX0 0 1
parent
Operation 0 0 0 1 0 1
001101
None
1
2
010101
3
011101
4
100101
5
101101
6
110101
7
111101
8
Logic “1” = VAH, VENH 2.4V
DG528
A2 A1 A0 EN WR RS
ON SWITCH
XXXX
1 Maintains Previous
Switch Condition
X X X X X 0 None (Latches Cleared)
XXX0 0 1
None
000101
1
001101
2
010101
3
011101
4
100101
5
101101
6
110101
7
111101
8
DG529
A1 A0 EN WR
XXX
XXX
XX0
001
011
101
111
Logic “1”: VAH 2.4V
Logic “0”: VAL 0.8V
X
0
0
0
0
0
RS ON SWITCH
1 Maintains Previous Switch
Condition
0 None (Latches Cleared)
1 None
11
12
13
14
12-12

12 Page





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