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DG423DK Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DG423DK
Beschreibung Improved Low-Power / CMOS Analog Switches with Latches
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 12 Seiten
DG423DK Datasheet, Funktion
19-0137; Rev 1; 3/94
Improved Low-Power,
CMOS Analog Switches with Latches
_______________General Description
Maxim’s redesigned DG421/DG423/DG425 monolithic
analog switches now feature guaranteed on-resistance
matching (3max) between switches and on-resistance
flatness over the signal range (4max). These low on-
resistance switches (20typ) conduct equally well in both
directions. They guarantee a low charge injection of 15pC
maximum and an ESD tolerance of 2000V minimum per
Method 3015.7. Off leakage current over temperature has
also been reduced (less than 5nA at +85°C).
The DG421/DG423/DG425 are precision, dual CMOS
switches with latchable logic inputs that simplify inter-
facing with microprocessors (µPs). The single-pole/single-
throw DG421 and double-pole/single-throw DG425 are
normally open dual switches. The dual, single-
pole/double-throw DG423 has two normally open and
two normally closed switches. Fast switching times
(175ns for tON and 145ns for tOFF) and low power
consumption (35µW max) make these parts ideal for
battery-powered applications requiring µP-compatible
switches. Operation is from a single +10V to +30V supply,
or bipolar ±4.5V to ±20V supplies. Fabricated with the
same 44V silicon-gate process, these switches have
rail-to-rail signal handling capabilities.
_______________________Applications
Sample-and-Hold Circuits
Fax Machines
Battery-Operated Systems
Guidance and Control Systems
Audio Signal Routing
Modems
Test Equipment
PBX, PABX
Military Radios
Communication Systems
__Functional Diagrams/Truth Tables
______________________New Features
o Plug-In Upgrades for Industry-Standard
DG421/DG423/DG425
o Improved r(DS)ON Match Between Channels (3max)
o Guaranteed rFLAT(ON) Over Signal Range (4max)
o Improved Charge Injection (15pC max)
o Improved Off Leakage Current Over Temperature
(<5nA at +85°C)
o Withstands Electrostatic Discharge (2000V min)
per Method 3015.7
__________________Existing Features
o Low rDS(ON) (35max)
o Single-Supply Operation +10V to +30V
Bipolar-Supply Operation ±4.5V to ±20V
o Low Power Consumption (35µW max)
o Rail-to-Rail Signal Handling Capability
o TTL/CMOS-Logic Compatible
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
DG421CJ
0°C to +70°C
16 Plastic DIP
DG421CY
0°C to +70°C
16 SO
DG421C/D
0°C to +70°C
Dice*
DG421DJ
-40°C to +85°C
16 Plastic DIP
DG421DY
-40°C to +85°C
16 SO
DG421DK
-40°C to +85°C
16 CERDIP
DG421AK
-55°C to +125°C
16 CERDIP**
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
**Contact factory for availability and processing to MIL-STD-883B.
_________________Pin Configurations
S1 D1
WR
IN1 CK
DQ
R
IN2 CK
DQ
RS R
S2
DG421
D2
TWO SPST SWITCHES
PER PACKAGE
DG421 TRUTH TABLE
WR RS IN SWITCH
0
0 11
Off
On
LOGIC "O" 0.8V
LOGIC "1" 2.4V
SWITCHES SHOWN FOR
LOGIC "1" INPUT
Functional Diagrams/Truth Tables continued at end of data sheet.
TOP VIEW
D1 1
WR 2
N.C. 3
N.C. 4
N.C. 5
N.C. 6
RS 7
D2 8
DG421
16 S1
15 IN1
14 V-
13 GND
12 VL
11 V+
10 IN2
9 S2
N.C. = No Internal Connection
DIP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.






DG423DK Datasheet, Funktion
Improved Low-Power,
CMOS Analog Switches with Latches
______________________________________________Timing Diagrams/Test Circuits
VOUT is the steady-state output with the switch on. Feedthrough via switch capacitance may result in spikes at the
leading and trailing edge of the output waveform.
LOGIC 3V
INPUT
0V
SWITCH 0V
OUTPUT
tR < 20ns
tF < 20ns
50%
tOFF
VOUT
0.9 x VOUT
tON
-VOUT
0.9 x VOUT
*VD = 10V for tON, VD = -10V for tOFF
NOTE: LOGIC INPUT WAVEFORM IS INVERTED FOR
SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
VD = 10V for tON
VD = -10V for tOFF
+5V
VL
D
IN
+15V
V+
S
RL
DG421
DG423
DG425
SWITCH OUTPUT
VOUT
CL
LOGIC
INPUT
GND V-
( )-15V
VOUT = VD
RL
RL + rDS(ON)
REPEAT TEST FOR IN2 AND S2.
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
3V
WR
0
3V
IN
0
3V
RS
0
SWITCH VOUT
OUTPUT 0
1.5V
tWW
tDW
2.0V
tWD
0.8V
1.5V
tRS
tOFF(RS)
0.8 x VOUT
Figure 3. Latch Timing
6 _______________________________________________________________________________________

6 Page









DG423DK pdf, datenblatt
Improved Low-Power,
CMOS Analog Switches with Latches
___________________________________________Package Information (continued)
A2
C
D1 D
e B1 B
D2
INCHES
DIM
MIN MAX
A 0.165 0.180
A1 0.100 0.110
A2 0.145 0.156
A3 0.020
B 0.013 0.021
B1 0.026 0.032
C 0.009 0.011
D 0.385 0.395
D1 0.350 0.355
D2 0.290 0.330
D3 0.200 REF
e 0.050 REF
MILLIMETERS
MIN MAX
4.19 4.57
2.54 2.79
3.68 3.96
0.51
0.33 0.53
0.66 0.81
0.23 0.28
9.78 10.03
8.89 9.02
7.37 8.38
5.08 REF
1.27 REF
21-981A
D3 A3
A1
D1
DA
20-PIN PLASTIC
LEADED CHIP
CARRIER
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.

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