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DG413 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer DG413
Beschreibung Monolithic Quad SPST / CMOS Analog Switches
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 13 Seiten
DG413 Datasheet, Funktion
®
Data Sheet
DG411, DG412, DG413
June 20, 2007
FN3282.13
Monolithic Quad SPST, CMOS Analog
Switches
The DG411 series monolithic CMOS analog switches are
drop-in replacements for the popular DG211 and DG212
series devices. They include four independent single pole
throw (SPST) analog switches, and TTL and CMOS
compatible digital inputs.
These switches feature lower analog ON-resistance (<35Ω)
and faster switch time (tON<175ns) compared to the DG211
or DG212. Charge injection has been reduced, simplifying
sample and hold applications.
The improvements in the DG411 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 40VP-P signals. Power supplies may be
single-ended from +5V to 44V, or split from ±5V to ±20V.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog
signals is quite low over a ±15V analog input range. The
switches in the DG411 and DG412 are identical, differing only
in the polarity of the selection logic. Two of the switches in the
DG413 (#2 and #3) use the logic of the DG211 and DG411
(i.e., a logic “0” turns the switch ON) and the other two
switches use DG212 and DG412 positive logic. This permits
independent control of turn-on and turn-off times for SPDT
configurations, permitting “break-before-make” or “make-
before-break” operation with a minimum of external logic.
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 35Ω
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <35µW
• Fast Switching Action
- tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175ns
- tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145ns
• Low Charge Injection
• Upgrade from DG211, DG212
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1993, 1994, 1997, 1999, 2002, 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






DG413 Datasheet, Funktion
DG411, DG412, DG413
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4)
UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 13.2V, V- = 0V
VIN = 0V or 5V
25 - 0.0001 1 μA
85 - - 5 μA
Negative Supply Current, I-
25
-1 -0.0001
-
μA
85 -5
-
- μA
Logic Supply Current, IL
25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND
25
-1 -0.0001
-
85 -5
-
-
μA
μA
NOTES:
3. VIN = input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
LOGIC
INPUT
3V
0V
SWITCH
INPUT
VS
SWITCH
OUTPUT 0V
50%
tOFF
VO 90%
tr < 20ns
tf < 20ns
90%
SWITCH
INPUT
S1
IN1
LOGIC
INPUT
+5V
VL
+15V
V+
D1
SWITCH
OUTPUT
VO
GND
V-
-15V
RL CL
tON
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENTS POINTS
Repeat test for all IN and S.
For load conditions, see Specifications. CL includes fixture and stray
capacitance.
VO
=
VS
---------------R-----L----------------
RL + rDS(ON)
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
LOGIC
INPUT
SWITCH
OUTPUT
(V01)
3V
0V
VS1
0V
VS2
90%
+5V +15V
VL V+
S1
VS1 = 10V
D1
S2
VS2 = 10V
IN1, IN2
D2
RL2
300Ω
VO2
RL1
300Ω
CL2
35pF
VO1
CL1
35pF
SWITCH
OUTPUT
VO2
0V
tD
90%
tD
LOGIC
INPUT
GND V-
-15V
CL includes fixture and
stray capacitance.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUITS
FIGURE 2. BREAK-BEFORE-MAKE TIME
6 FN3282.13
June 20, 2007

6 Page









DG413 pdf, datenblatt
DG411, DG412, DG413
Dual-In-Line Plastic Packages (PDIP)
INDEX
AREA
N
12 3
E1
N/2
-A-
BASE
PLANE
SEATING
PLANE
D1
B1
B
-B-
D
-C- A2 A
L
D1
e
A1
eC
0.010 (0.25) M C A B S
E
CL
eA
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendic-
ular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115 0.195 2.93
4.95
-
B
0.014 0.022 0.356 0.558
-
B1 0.045 0.070 1.15 1.77 8, 10
C
0.008 0.014 0.204 0.355
-
D
0.735 0.775 18.66 19.68
5
D1
0.005
-
0.13
-
5
E
0.300 0.325 7.62
8.25
6
E1
0.240 0.280 6.10
7.11
5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC
7.62 BSC
6
eB - 0.430 - 10.92 7
L
0.115 0.150 2.93
3.81
4
N 16
16 9
Rev. 0 12/93
12 FN3282.13
June 20, 2007

12 Page





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