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DG405 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer DG405
Beschreibung Monolithic CMOS Analog Switches
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
DG405 Datasheet, Funktion
Data Sheet
DG401, DG403, DG405
June 1999 File Number 3284.6
Monolithic CMOS Analog Switches
The DG401, DG403 and DG405 monolithic CMOS analog
switches have TTL and CMOS compatible digital inputs.
These switches feature low analog ON resistance (<45)
and fast switch time (tON < 150ns). Low charge injection
simplifies sample and hold applications.
The improvements in the DG401/403/405 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 30VP-P signals. Power supplies may be
single-ended from +5V to +34V, or split from ±5V to ±17V.
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a ±15V analog input range. The three
different devices provide the equivalent of two SPST (DG401),
two SPDT (DG403) or two DPST (DG405) relay switch
contacts with CMOS or TTL level activation. The pinout is
similar, permitting a standard layout to be used, choosing the
switch function as needed.
Pinouts
DG401 (PDIP, SOIC)
TOP VIEW
D1 1
NC 2
NC 3
NC 4
NC 5
NC 6
NC 7
D2 8
16 S1
15 IN1
14 V-
13 GND
12 VL
11 V+
10 IN2
9 S2
DG403, DG405 (SOIC)
TOP VIEW
D1 1
NC 2
D3 3
S3 4
S4 5
D4 6
NC 7
D2 8
16 S1
15 IN1
14 V-
13 GND
12 VL
11 V+
10 IN2
9 S2
Features
• ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 45
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <35µW
• Fast Switching Action
- tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
- tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns
• Low Charge Injection
• DG401 Dual SPST; Same Pinout as HI-5041
• DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
• DG405 Dual DPST; DG184, HI-5045, IH5145
• TTL, CMOS Compatible
• Single or Split Supply Operation
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG. NO.
DG401DJ
-40 to 85 16 Ld PDIP E16.3
DG401DY
-40 to 85 16 Ld SOIC M16.15
DG403DJ
-40 to 85 16 Ld PDIP E16.3
DG403DY
-40 to 85 16 Ld SOIC M16.15
DG405DY
-40 to 85 16 Ld SOIC M16.15
TRUTH TABLE
DG401
DG403
LOGIC SWITCH SWITCH 1, 2 SWITCH 3, 4
0 OFF
OFF
ON
1 ON ON OFF
NOTE: Logic “0” 0.8V. Logic “1” 2.4V.
DG405
SWITCH
OFF
ON
NOTE: (NC) No Connection.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






DG405 Datasheet, Funktion
DG401, DG403, DG405
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C1
or C2. Another one selects eIN or discharges the capacitor in
preparation for the next integration cycle.
+5V +15V
VL V+
eIN S1
S3
D1
D2
INTEGRATE/
RESET
TTL
SCOPE
SELECT
IN1
S2 D3 C1
S4 D4
IN2 C2
DG403
GND
V-
-15V
eOUT
Peak Detector
A3 acting as a comparator provides the logic drive for
operating SW1. The output of A2 is fed back to A3 and
compared to the analog input eIN. If eIN > eOUT the output
of A3 is high keeping SW1 closed. This allows C1 to charge
up to the analog input voltage. When eIN goes below eOUT,
A3 goes negative, turning SW1 off. The system will therefore
store the most positive analog input experienced.
RESET
+- A1
eIN
+
-
A3
SW2
SW1
R1
DG401
C1
A2 eOUT
+
-
FIGURE 8. DUAL SLOPE INTEGRATOR
FIGURE 9. POSITIVE PEAK DETECTOR
Typical Performance Curves
10
V+ = 15V
V- = -15V
8 TA = 20oC
6
DG403
4 SW3, 4
2
0
0 2 4 6 8 10 12 14 16 18 20
VL (V)
FIGURE 10. INPUT SWITCHING THRESHOLD vs LOGIC
SUPPLY VOLTAGE
4
VL
TA
=
=
5V
25oC
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (±V)
FIGURE 11. INPUT SWITCHING THRESHOLD vs
POWER SUPPLY VOLTAGE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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