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DG201AK Schematic ( PDF Datasheet ) - Harris Corporation

Teilenummer DG201AK
Beschreibung CMOS Dual/Quad SPST Analog Switches
Hersteller Harris Corporation
Logo Harris Corporation Logo 




Gesamt 8 Seiten
DG201AK Datasheet, Funktion
SEMICONDUCTOR
DG200, DG201
December 1993
CMOS Dual/Quad SPST Analog Switches
Features
Description
• Switches Greater than 28VP-P Signals with ±15 Supplies
• Break-Before-Make Switching tOFF 250ns, tON 700ns
Typical
• TTL, DTL, CMOS, PMOS Compatible
• Non-Latching with Supply Turn-Off
• Complete Monolithic Construction
• Industry Standard (DG200, DG201)
The DG200 and DG201 solid state analog gates are
designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latch-up of solid state analog gates
has been eliminated by Harris's CMOS technology.
The DG200 and DG201 are completely specification and
pinout compatible with the industry standard devices.
Applications
• Data Acquisition
• Sample and Hold Circuits
• Operational Amplifier Gain Switching Networks
Ordering Information
PART NUMBER
DG200AA
DG200AK
DG200BA
DG200BK
DG200CJ
DG200AA/883B
DG200AK/883B
DG201AK
DG201BK
DG201CJ
DG201AK/883B
TEMPERATURE
-55oC to +125oC
-55oC to +125oC
-25oC to +85oC
-25oC to +85oC
0oC to +70oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-25oC to +85oC
0oC to +70oC
-55oC to +125oC
PACKAGE
10 Pin Metal Can
14 Lead Ceramic DIP
10 Pin Metal Can
14 Lead Ceramic DIP
14 Lead Plastic DIP
10 Pin Metal Can
14 Lead Ceramic DIP
16 Lead Ceramic DIP
16 Lead Ceramic DIP
16 Lead Plastic DIP
16 Lead Ceramic DIP
Pinouts
DG200
(CDIP, PDIP)
TOP VIEW
IN2 1
NC 2
GND 3
NC 4
S2 5
D2 6
V- 7
14 IN1
13 NC
12 V+ (SUBSTRATE)
11 NC
10 S1
9 D1
8 VREF
DG200
(TO-100 METAL CAN)
TOP VIEW
V+
(SUBSTRATE AND CASE)
10
IN1 1
9 S1
IN2 2
8 D1
GND 3
S2 4
7 VREF
5 6 V-
D2
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
DG201
(CDIP, PDIP)
TOP VIEW
16 IN2
15 D2
14 S2
13 V+(SUBSTRATE)
12 VREF
11 S3
10 D3
9 IN3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993
9-13
File Number 3115






DG201AK Datasheet, Funktion
Test Circuits
DG200, DG201
ANALOG
INPUT 10V
3V
0V
LOGIC
INPUT
2k
10pF
VOUT
1k
NOTE: All channels are turned off by high “1” logic inputs and
all channels are turned on by low “0” inputs; however 0.8V to
2.4V describes the minimum range for switching properly.
Peak input current required for transition is typically -120µA.
FIGURE 5.
3V
0V
LOGIC
INPUT
LOGIC
INPUT *
2VP-P AT 1MHz
ANALOG
INPUT 10V
10,000pF
VOUT
FIGURE 6.
51
VOUT
100
* Pull Down Resistor must be 2k.
FIGURE 7.
Typical Applications
Using the VREF Terminal
The DG200 and DG201 have an internal voltage divider set-
ting the TTL threshold on the input control lines for V+ equal
to +15V. The schematic shown in Figure 8 with nominal
resistor values, gives approximately 2.4V on the VREF pin.
As the TTL input signal goes from +0.8V to +2.4V, Q1 and
Q2 switch states to turn the switch ON and OFF.
V+ (+15V)
If the power supply voltage is less than +15V, then a resistor
must be added between V+ and the VREF pin, to restore
+2.4V at VREF. The table shows the value of this resistor for
various supply voltages, to maintain TTL compatibility. If
CMOS logic levels on a +5V supply are being used, the
threshold shifts are less critical, but a separate column of
suitable values is given in the table. For logic swings of -5V
to + 5V, no resistor is needed.
In general, the “low” logic level should be <0.8V to prevent
Q1 and Q2 from both being ON together (this will cause
incorrect switch function).
31k
REXT
Q1 VREF
6k
GATE
PROTECTION
RESISTOR
Q2
V+ SUPPLY (V)
+15
+12
+10
+9
+8
+7
TABLE 1.
TTL RESISTOR
(k)
-
100
51
(34)
(27)
18
CMOS RESISTOR
(k)
-
-
-
34
27
18
INPUT
FIGURE 8.
9-18

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