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DG201A Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer DG201A
Beschreibung Quad SPST / CMOS Analog Switches
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 7 Seiten
DG201A Datasheet, Funktion
Data Sheet
DG201A, DG202
June 1999 File Number 3117.2
Quad SPST, CMOS Analog Switches
The DG201A and DG202 quad SPST analog switches are
designed using Intersil’s 44V CMOS process. These
bidirectional switches are latch-proof and feature break-
before-make switching. Designed to block signals up to
30VP-P in the OFF state, the DG201A and DG202 offer the
advantages of low ON resistance (175), wide input signal
range (±15V) and provide both TTL and CMOS compatibility.
The DG201A and DG202 are specification and pinout
compatible with the industry standard devices.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
DG201AAK
-55 to 125 16 Ld CERDIP
DG201ABK
-25 to 85 16 Ld CERDIP
DG201ACJ
0 to 70 16 Ld PDIP
DG201ACY
0 to 70 16 Ld SOIC
DG202AK
-55 to 125 16 Ld CERDIP
DG202CJ
0 to 70 16 Ld PDIP
PKG.
NO.
F16.3
F16.3
E16.3
M16.3
F16.3
E16.3
Pinout
DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
16 IN2
15 D2
14 S2
13
V+ (SUB-
S- TRATE)
12 NC
11 S3
10 D3
9 IN3
Features
• Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Low rDS(ON) (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . 175
• TTL, CMOS Compatible
• Latch-Up Proof
• True Second Source
• Maximum Supply Ratings. . . . . . . . . . . . . . . . . . . . . . 44V
• Logic Inputs Accept Negative Voltages
Functional Block Diagrams
DG201A
S1
IN1
D1
S2
IN2
D2
S3
IN3
D3
S4
IN4
D4
DG202
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
SWITCHES SHOWN FOR LOGIC “1” INPUT
TRUTH TABLE
LOGIC
DG201A
DG202
0 ON
1 OFF
Logic “0” 0.8V, Logic “1” 2.4V
OFF
ON
4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






DG201A Datasheet, Funktion
DG201A, DG202
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A- -D-
E
-B-
bbb S C A - B S D S
c1 LEAD FINISH
BASE
METAL
(c)
b1
MM
(b)
SECTION A-A
BASE
PLANE
SEATING
PLANE
S1
b2
b
D
AA
e
Q
-C- A
L
eA/2
α
eA
c
ccc M C A - B S D S
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
- 0.200 - 5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D - 0.840 - 21.34 5
E
0.220
0.310
5.59
7.87
5
e 0.100 BSC
2.54 BSC
-
eA 0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1 0.005 - 0.13 - 7
α
90o 105o 90o 105o
-
aaa
- 0.015 - 0.38
-
bbb
- 0.030 - 0.76
-
ccc
- 0.010 - 0.25
-
M
-
0.0015
-
0.038
2, 3
N 16
16 8
Rev. 0 4/94
4-6

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