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DG181BA Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer DG181BA
Beschreibung High-Speed Drivers with JFET Switch
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
DG181BA Datasheet, Funktion
Semiconductor
DG181 thru DG191
April 1999
Features
• Constant
ON-PROeDSDsDGiSGsG1OtI1Ba189Bn9L40cS1,E:e:ODDSHfGLoGUIEr1-B45T8S00S5Ei34g:T,3PnHIHT,aRIHUlI-Os-55IT-0Dt00Eo4U539P1±9C,,1R0HTI0,OHIVI-HD55(150UD504CG145T1382,
DG185, DG188, DG191), to ±7.5V (All Devices)
±15V Power Supplies
• <2nA Leakage from Signal Channel in Both ON and
OFF States
• TTL, DTL, RTL Direct Drive Compatibility
• tON, tOFF <150ns, Break-Before-Make Action
• Cross-Talk and Open Switch Isolation >50dB at 10MHz
(75Load)
High-Speed Drivers with JFET Switch
Description
The DG181 thru DG191 series of analog gates consist of 2
or 4 N-channel junction-type field-effect transistors (JFET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8V to 2V) to control the
ON-OFF state of each switch. The driver is designed to
provide a turn-off speed which is faster than turn-on speed,
so that break-before-make action is achieved when
switching from one channel to another. In the ON state, each
switch conducts current equally well in both directions. In the
OFF condition, the switches will block voltages up to 20V
peak-to-peak. Switch-OFF input-output isolation 50dB at
10MHz, due to the low output impedance of the FET-gate
driving circuit.
Functional Diagrams (Typical Channel)
DG186, DG187, DG188 - ONE AND TWO CHANNEL
SPDT AND SPST CIRCUIT CONFIGURATION
VL V+
DG183, DG184, DG185 - TWO CHANNEL DPST
CIRCUIT CONFIGURATION
VL V+
IN
GND V-
S1 IN
D1
S2
D2
GND
V-
S
D
S
D
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1999
1
File Number 3114.4






DG181BA Datasheet, Funktion
DG181 Series
DUAL SPST - DG181/182
TEST CONDITIONS
VIN “ON” = 0.8V
All Channels
VIN “OFF” = 2.0V
All Channels
NOTE:
1. Switch states are for logic “1” input = 2.0V.
DUAL DPST - DG184/185
TEST CONDITIONS
VIN “ON” = 2.0V
All Channels
VIN “OFF” = 0.8V
All Channels
NOTE:
1. Switch states are for logic “1” input = 2.0V.
SPDT - DG187/188
TEST CONDITIONS
VIN “ON” = 2.0V
Channel 1
VIN “ON” = 0.8V
Channel 2
VIN “OFF” = 2.0V
Channel 2
VIN “OFF” = 0.8V
Channel 1
NOTE:
1. Switch states are for logic “1” input = 2.0V.
SPDT - DG190/191
TEST CONDITIONS
VIN “ON” = 2.0V
Channel 1 and 2
VIN “ON” = 0.8V
Channel 3 and 4
VIN “OFF” = 2.0V
Channel 3 and 4
VIN “OFF” = 0.8V
Channel 1 and 2
NOTE:
1. Switch states are for logic “1” input = 2.0V.
Switching Time Test Circuits
LOGIC 3V
INPUT
tR < 10ns
tF < 10ns
0V
SWITCH
INPUT
VS
SWITCH 0V
OUTPUT
50%
90%
t ON
50%
90%
t OFF
+5V
VL
SWITCH S1
INPUT
tON, VS = +10V
tOFF, VS = -10V
LOGIC
INPUT
IN1
GND
0V
+15V
VCC
D1
RL
1k
SWITCH
OUTPUT
VO
CL
30pF
(REPEAT TEST FOR
V-
-15V
ALL CHANNELS)
RL
VO = VS RL + RDS(ON)
FIGURE 1. SWITCHING TIME TEST WAVEFORMS (Note 1)
FIGURE 2. SWITCHING TIME TEST CIRCUIT (Note 2)
NOTES:
1. Switch output waveform shown for VS = constant with logic input waveform as shown.
2. VS may be + or - as per switching time test circuit. VO is the steady state output with switch on. Feedthrough via gate capacitance may
result in spikes at leading and trailing edge of output waveform.
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